RISC-V: testsuite: Fix DejaGnu support for riscv_zvfh

Call check_effective_target_riscv_zvfh_ok rather than
check_effective_target_riscv_zvfh in vx_vf_*run-1-f16.c run tests and ensure
that they are actually run.
Also fix remove_options_for_riscv_zvfh.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c: Call
	check_effective_target_riscv_zvfh_ok rather than
	check_effective_target_riscv_zvfh.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c: Likewise.
	* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c: Likewise.
	* lib/target-supports.exp (check_effective_target_riscv_zvfh_ok): Append
	zvfh instead of v to march.
	(remove_options_for_riscv_zvfh): Remove duplicate and
	call remove_ rather than add_options_for_riscv_z_ext.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
index fd8aa30be17a3bd3276f61f6f46cc01e25dad430..a54d9a12ecdcd40f69f24281c7f79c94ac648683 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
index 8fd8552889930f346378c47ecdd1509a902c3654..2289d04e91d4e06c7545b73ceb51d2112e0ade0e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
index e91fd15a5b7307bc114fc7d8fb49a6c8d8176a39..b6d944cf945fdb28c389ff2e02f21a3fd39122b6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
index ca7e0db17b5b5385129a8bee5e0f97b6f3db5fdd..e9253fe407c724973e2c722b62c4afb819499154 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
index b38e8009fd8f8f282edc303416809e6a4f581253..397e2834e29ce14d1ac7010cbed3dfc6c912b6c5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
index fef5d7779a2887e8ccdf26e0c189752632fbeb97..6d846a23af7b34c9365a93f1fa343222770ce455 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
index 7951d402c1e776cd688d774d5766e15d400df258..0b4f6e1056894a0c8017133ecfaace34c6b110aa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
index d0def86acc520c1f2116273c55c4bf731175492d..acc7aa35ebf9c5d1c6afca80587feafe0dfed294 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
index d4c527abd36c9c114a7e8debf45df064f1f40358..a858d27119b842b1a1d3d05d70d6a053a5fba77a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
index abce2f2c408dc8cae119c76d8971d5e83a8c60d9..a04bd91213a10052dbe2a755e3bb6a1f2f0aa15d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
index ddf49d5b2f23c5c0411f601d89b75e732164e5d1..a00d6206fd9475bdf0aeabd7afa8fd479422486e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
index a8749915569af8c8f540977ea6cb46e28576d20b..eeae215c80f1870aaf4406d0c4c51e461296b56d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
 /* { dg-add-options "riscv_v" } */
 /* { dg-add-options "riscv_zvfh" } */
 /* { dg-additional-options "--param=fpr2vr-cost=0" } */

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index e8f8885259171e826b1d9b8feb8d432e7df310c5..b49363caa12b287780f8131c0efdbb2823508dfb 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2342,7 +2342,7 @@ proc check_effective_target_riscv_zvfh_ok { } {
 
     # check if we can execute vector insns with the given hardware or
     # simulator
-    set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v]
+    set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &zvfh]
     if { [check_runtime ${gcc_march}_zvfh_exec {
        int main()
        {
@@ -2711,10 +2711,6 @@ proc remove_options_for_riscv_ztso { flags } {
     return [remove_options_for_riscv_z_ext ztso $flags]
 }
 
-proc remove_options_for_riscv_zvfh { flags } {
-    return [add_options_for_riscv_z_ext zvfh $flags]
-}
-
 proc add_options_for_riscv_zvbb { flags } {
     return [add_options_for_riscv_z_ext zvbb $flags]
 }
@@ -2728,7 +2724,7 @@ proc add_options_for_riscv_zvfh { flags } {
 }
 
 proc remove_options_for_riscv_zvfh { flags } {
-    return [add_options_for_riscv_z_ext zvfh $flags]
+    return [remove_options_for_riscv_z_ext zvfh $flags]
 }
 
 # Return 1 if the target is ia32 or x86_64.