Xilinx: ARM: Removed M29EW Flash init code in board

Removed pl353 parameter initialization code for M29EW Flash.
This might have been added during initial support of u-boot.

pl353 controller specific timing info was initialized
prior to u-boot stage hence it is being removed.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

diff --git a/board/xilinx/zynq_common/board.c b/board/xilinx/zynq_common/board.c
index 35d4bcc4cb918423e2a6386122020730ca491e00..64a284edf96e76dbbce54475e9a2c2404def12bb 100644 (file)
--- a/board/xilinx/zynq_common/board.c
+++ b/board/xilinx/zynq_common/board.c
@@ -8,13 +8,6 @@
 #include <netdev.h>
 #include <zynqpl.h>
 
-#define PARPORT_CRTL_BASEADDR                   XPSS_CRTL_PARPORT_BASEADDR
-#define NOR_FLASH_BASEADDR                      XPSS_PARPORT0_BASEADDR
-
-#define PARPORT_MC_DIRECT_CMD                   0x010
-#define PARPORT_MC_SET_CYCLES                   0x014
-#define PARPORT_MC_SET_OPMODE                   0x018
-
 #define BOOT_MODE_REG     (XPSS_SYS_CTRL_BASEADDR + 0x25C)
 #define BOOT_MODES_MASK    0x0000000F
 #define QSPI_MODE         (0x00000001)            /**< QSPI */
@@ -40,16 +33,6 @@ static u32 In32(u32 InAddress)
     return temp;
 }
 
-static inline void Out8(u32 OutAddress, u8 Value)
-{
-    *(volatile u8 *) OutAddress = Value;
-}
-
-static inline u8 In8(u32 InAddress)
-{
-    return *(u8 *) InAddress;
-}
-
 /* Common IO for xgmac and xnand */
 /* Data Memory Barrier */
 #define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
@@ -68,56 +51,6 @@ u32 XIo_In32(u32 InAddress)
        return temp;
 }
 
-#ifndef CONFIG_SYS_NO_FLASH
-/*
- * init_nor_flash init the parameters of pl353 for the M29EW Flash
- */
-void init_nor_flash(void)
-{
-  /* Init variables */
-
-   /* Write timing info to set_cycles registers */
-  u32 set_cycles_reg = (0x0 << 20) | /* Set_t6 or we_time from sram_cycles */
-                       (0x1 << 17) | /* Set_t5 or t_tr from sram_cycles */
-                       (0x2 << 14) | /* Set_t4 or t_pc from sram_cycles */
-                       (0x5 << 11) | /* Set_t3 or t_wp from sram_cycles */
-                       (0x2 << 8) |  /* Set_t2 t_ceoe from sram_cycles */
-                       (0x7 << 4) |  /* Set_t1 t_wc from sram_cycles */
-                       (0x7);        /* Set_t0 t_rc from sram_cycles */
-
-  Out32(PARPORT_CRTL_BASEADDR + PARPORT_MC_SET_CYCLES, set_cycles_reg);
-
-  /* write operation mode to set_opmode registers */
-  u32 set_opmode_reg = (0x1 << 13) | /* set_burst_align, see to 32 beats */
-                       (0x1 << 12) | /* set_bls, set to default */
-                       (0x0 << 11) | /* set_adv bit, set to default */
-                       (0x0 << 10) | /* set_baa, I guess we don't use baa_n */
-                       (0x0 << 7) |  /* set_wr_bl, write brust length, set to 0 */
-                       (0x0 << 6) |  /* set_wr_sync, set to 0 */
-                       (0x0 << 3) |  /* set_rd_bl, read brust lenght, set to 0 */
-                       (0x0 << 2) |  /* set_rd_sync, set to 0 */
-                       (0x0 );       /* set_mw, memory width, 16bits width*/
-  Out32(PARPORT_CRTL_BASEADDR + PARPORT_MC_SET_OPMODE, set_opmode_reg);
-
-  /*
-   * Issue a direct_cmd by writing to direct_cmd register
-   * This is needed becuase the UpdatesReg flag in direct_cmd updates the
-   * state of SMC
-   */
-  u32 direct_cmd_reg = (0x0 << 23) | /* chip 1 from interface 0 */
-                       (0x2 << 21) | /* UpdateRegs operation, to update the two reg we wrote earlier*/
-                       (0x0 << 20) | /* cre */
-                       (0x0);        /* addr, not use in UpdateRegs */
-  Out32(PARPORT_CRTL_BASEADDR + PARPORT_MC_DIRECT_CMD, direct_cmd_reg);
-
-  /* reset the flash itself so that it's ready to be accessed */
-
-  Out8(NOR_FLASH_BASEADDR + 0xAAA, 0xAA);
-  Out8(NOR_FLASH_BASEADDR + 0x555, 0x55);
-  Out8(NOR_FLASH_BASEADDR,         0xF0);
-}
-#endif
-
 #define Xil_Out32 Out32
 #define Xil_In32 In32
 
@@ -142,9 +75,6 @@ int board_init(void)
        Xil_Out32(0xe000a040, 0x80);
 
        icache_enable();
-#ifndef CONFIG_SYS_NO_FLASH
-       init_nor_flash();
-#endif
 
 #ifdef CONFIG_FPGA
        fpga_init();