ddr: imx: Add 3600 MTps rate support

Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps
PLL setting, except the divider is not 9 but 8 .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 986870799d367c8eb581c16c6d207dbc0b9cc07c..a24eb7446015abf6d1f65900ac948e4195e75414 100644 (file)
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -56,6 +56,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
        PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
        PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
+       PLL_1443X_RATE(900000000U, 300, 8, 0, 0),
        PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
        PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
        PLL_1443X_RATE(650000000U, 325, 3, 2, 0),

diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index d5dac0fce9240aa2205852bb6c056580f1ce3a5b..45e1a70dbd44d23151fd5e13c3ea91c1851921de 100644 (file)
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -117,6 +117,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
                dram_pll_init(MHZ(933));
                dram_disable_bypass();
                break;
+       case 3600:
+               dram_pll_init(MHZ(900));
+               dram_disable_bypass();
+               break;
        case 3200:
                dram_pll_init(MHZ(800));
                dram_disable_bypass();