*/
if (mc->valid_cpu_types) {
assert(mc->valid_cpu_types[0] != NULL);
+ assert(!mc->get_valid_cpu_types);
+
for (i = 0; mc->valid_cpu_types[i]; i++) {
if (object_class_dynamic_cast(oc, mc->valid_cpu_types[i])) {
break;
error_append_hint(errp, "\n");
}
+ return false;
+ }
+ } else if (mc->get_valid_cpu_types) {
+ GPtrArray *vct = mc->get_valid_cpu_types(machine);
+ bool valid = false;
+
+ for (i = 0; i < vct->len; i++) {
+ if (object_class_dynamic_cast(oc, vct->pdata[i])) {
+ valid = true;
+ break;
+ }
+ }
+
+ if (!valid) {
+ g_autofree char *requested = cpu_model_from_type(machine->cpu_type);
+
+ error_setg(errp, "Invalid CPU model: %s", requested);
+ error_append_hint(errp, "The valid models are: ");
+ for (i = 0; i < vct->len; i++) {
+ g_autofree char *model = cpu_model_from_type(vct->pdata[i]);
+ error_append_hint(errp, "%s%s",
+ model, i + 1 == vct->len ? "\n" : ", ");
+ }
+ }
+ g_ptr_array_free(vct, true);
+ if (!valid) {
return false;
}
}
* @smbios_memory_device_size:
* Default size of memory device,
* SMBIOS 3.1.0 "7.18 Memory Device (Type 17)"
+ * @get_valid_cpu_types:
+ * Returns a list of valid CPU types for this board. May be NULL
+ * if not needed.
*/
struct MachineClass {
/*< private >*/
bool ignore_memory_transaction_failures;
int numa_mem_align_shift;
const char * const *valid_cpu_types;
+ GPtrArray *(*get_valid_cpu_types)(const MachineState *ms);
strList *allowed_dynamic_sysbus_devices;
bool auto_enable_numa_with_memhp;
bool auto_enable_numa_with_memdev;