octeontx2-af: Fix NIX SQ mode and BP config

[ Upstream commit faf23006185e777db18912685922c5ddb2df383f ]

NIX SQ mode and link backpressure configuration is required for
all platforms. But in current driver this code is wrongly placed
under specific platform check. This patch fixes the issue by
moving the code out of platform check.

Fixes: 5d9b976d4480 ("octeontx2-af: Support fixed transmit scheduler topology")
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Link: https://lore.kernel.org/r/20240408063643.26288-1-gakula@marvell.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index e549b09c347a769400f987aeb3f96d8e6d21de83..fb4b18be503c5358ef5e289b79489c71e53e10a0 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -3146,18 +3146,18 @@ int rvu_nix_init(struct rvu *rvu)
                 */
                rvu_write64(rvu, blkaddr, NIX_AF_CFG,
                            rvu_read64(rvu, blkaddr, NIX_AF_CFG) | 0x40ULL);
+       }
 
-               /* Set chan/link to backpressure TL3 instead of TL2 */
-               rvu_write64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL, 0x01);
+       /* Set chan/link to backpressure TL3 instead of TL2 */
+       rvu_write64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL, 0x01);
 
-               /* Disable SQ manager's sticky mode operation (set TM6 = 0)
-                * This sticky mode is known to cause SQ stalls when multiple
-                * SQs are mapped to same SMQ and transmitting pkts at a time.
-                */
-               cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS);
-               cfg &= ~BIT_ULL(15);
-               rvu_write64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS, cfg);
-       }
+       /* Disable SQ manager's sticky mode operation (set TM6 = 0)
+        * This sticky mode is known to cause SQ stalls when multiple
+        * SQs are mapped to same SMQ and transmitting pkts at a time.
+        */
+       cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS);
+       cfg &= ~BIT_ULL(15);
+       rvu_write64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS, cfg);
 
        ltdefs = rvu->kpu.lt_def;
        /* Calibrate X2P bus to check if CGX/LBK links are fine */