--- /dev/null
+From stable+bounces-87982-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:01 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:37:54 -0700
+Subject: drm/i915: disable fbc due to Wa_16023588340
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Matthew Auld <matthew.auld@intel.com>, Jonathan Cavitt <jonathan.cavitt@intel.com>, Matt Roper <matthew.d.roper@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>, Vinod Govindapillai <vinod.govindapillai@intel.com>, Jani Nikula <jani.nikula@intel.com>, intel-gfx@lists.freedesktop.org
+Message-ID: <20241024033815.3538736-2-lucas.demarchi@intel.com>
+
+From: Matthew Auld <matthew.auld@intel.com>
+
+commit c55f79f317ab428ae6d005965bc07e37496f209f upstream.
+
+On BMG-G21 we need to disable fbc due to complications around the WA.
+
+v2:
+ - Try to handle with i915_drv.h and compat layer. (Rodrigo)
+v3:
+ - For simplicity retreat back to the original design for now.
+ - Drop the extra \ from the Makefile (Jani)
+
+Signed-off-by: Matthew Auld <matthew.auld@intel.com>
+Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
+Cc: Matt Roper <matthew.d.roper@intel.com>
+Cc: Lucas De Marchi <lucas.demarchi@intel.com>
+Cc: Vinod Govindapillai <vinod.govindapillai@intel.com>
+Cc: Jani Nikula <jani.nikula@intel.com>
+Cc: intel-gfx@lists.freedesktop.org
+Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
+Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240703124338.208220-4-matthew.auld@intel.com
+[ commit dc0f1644c47e ("drm/xe: Generate oob before compiling anything")
+ makes part of the change to the Makefile not needed.
+ Drop that to resolve conflict. ]
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_display_wa.h | 8 ++++++++
+ drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++++
+ drivers/gpu/drm/xe/Makefile | 1 +
+ drivers/gpu/drm/xe/display/xe_display_wa.c | 16 ++++++++++++++++
+ 4 files changed, 31 insertions(+)
+ create mode 100644 drivers/gpu/drm/xe/display/xe_display_wa.c
+
+--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
++++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
+@@ -6,8 +6,16 @@
+ #ifndef __INTEL_DISPLAY_WA_H__
+ #define __INTEL_DISPLAY_WA_H__
+
++#include <linux/types.h>
++
+ struct drm_i915_private;
+
+ void intel_display_wa_apply(struct drm_i915_private *i915);
+
++#ifdef I915
++static inline bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915) { return false; }
++#else
++bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915);
++#endif
++
+ #endif
+--- a/drivers/gpu/drm/i915/display/intel_fbc.c
++++ b/drivers/gpu/drm/i915/display/intel_fbc.c
+@@ -56,6 +56,7 @@
+ #include "intel_display_device.h"
+ #include "intel_display_trace.h"
+ #include "intel_display_types.h"
++#include "intel_display_wa.h"
+ #include "intel_fbc.h"
+ #include "intel_fbc_regs.h"
+ #include "intel_frontbuffer.h"
+@@ -1237,6 +1238,11 @@ static int intel_fbc_check_plane(struct
+ return 0;
+ }
+
++ if (intel_display_needs_wa_16023588340(i915)) {
++ plane_state->no_fbc_reason = "Wa_16023588340";
++ return 0;
++ }
++
+ /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
+ if (i915_vtd_active(i915) && (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
+ plane_state->no_fbc_reason = "VT-d enabled";
+--- a/drivers/gpu/drm/xe/Makefile
++++ b/drivers/gpu/drm/xe/Makefile
+@@ -175,6 +175,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
+ display/xe_display.o \
+ display/xe_display_misc.o \
+ display/xe_display_rps.o \
++ display/xe_display_wa.o \
+ display/xe_dsb_buffer.o \
+ display/xe_fb_pin.o \
+ display/xe_hdcp_gsc.o \
+--- /dev/null
++++ b/drivers/gpu/drm/xe/display/xe_display_wa.c
+@@ -0,0 +1,16 @@
++// SPDX-License-Identifier: MIT
++/*
++ * Copyright © 2024 Intel Corporation
++ */
++
++#include "intel_display_wa.h"
++
++#include "xe_device.h"
++#include "xe_wa.h"
++
++#include <generated/xe_wa_oob.h>
++
++bool intel_display_needs_wa_16023588340(struct drm_i915_private *i915)
++{
++ return XE_WA(xe_root_mmio_gt(i915), 16023588340);
++}
--- /dev/null
+From stable+bounces-87983-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:02 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:37:55 -0700
+Subject: drm/i915/display: Cache adpative sync caps to use it later
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>, Arun R Murthy <arun.r.murthy@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-3-lucas.demarchi@intel.com>
+
+From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+
+commit b2013783c4458a1fe8b25c0b249d2e878bcf6999 upstream.
+
+Add new member to struct intel_dp to cache support of Adaptive Sync
+SDP capabilities and use it whenever required to avoid HW access
+to read capability during each atomic commit.
+
+-v2:
+- Squash both the patches
+
+Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240704082638.2302092-2-mitulkumar.ajitkumar.golani@intel.com
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_alpm.c | 2 -
+ drivers/gpu/drm/i915/display/intel_display_types.h | 1
+ drivers/gpu/drm/i915/display/intel_dp.c | 22 +++++++++++----------
+ drivers/gpu/drm/i915/display/intel_dp.h | 1
+ drivers/gpu/drm/i915/display/intel_vrr.c | 3 --
+ 5 files changed, 15 insertions(+), 14 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_alpm.c
++++ b/drivers/gpu/drm/i915/display/intel_alpm.c
+@@ -280,7 +280,7 @@ void intel_alpm_lobf_compute_config(stru
+ if (DISPLAY_VER(i915) < 20)
+ return;
+
+- if (!intel_dp_as_sdp_supported(intel_dp))
++ if (!intel_dp->as_sdp_supported)
+ return;
+
+ if (crtc_state->has_psr)
+--- a/drivers/gpu/drm/i915/display/intel_display_types.h
++++ b/drivers/gpu/drm/i915/display/intel_display_types.h
+@@ -1806,6 +1806,7 @@ struct intel_dp {
+
+ /* connector directly attached - won't be use for modeset in mst world */
+ struct intel_connector *attached_connector;
++ bool as_sdp_supported;
+
+ struct drm_dp_tunnel *tunnel;
+ bool tunnel_suspended:1;
+--- a/drivers/gpu/drm/i915/display/intel_dp.c
++++ b/drivers/gpu/drm/i915/display/intel_dp.c
+@@ -130,14 +130,6 @@ bool intel_dp_is_edp(struct intel_dp *in
+ return dig_port->base.type == INTEL_OUTPUT_EDP;
+ }
+
+-bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp)
+-{
+- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+-
+- return HAS_AS_SDP(i915) &&
+- drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
+-}
+-
+ static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+
+ /* Is link rate UHBR and thus 128b/132b? */
+@@ -2635,8 +2627,7 @@ static void intel_dp_compute_as_sdp(stru
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+- if (!crtc_state->vrr.enable ||
+- !intel_dp_as_sdp_supported(intel_dp))
++ if (!crtc_state->vrr.enable || intel_dp->as_sdp_supported)
+ return;
+
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+@@ -5921,6 +5912,15 @@ intel_dp_detect_dsc_caps(struct intel_dp
+ connector);
+ }
+
++static void
++intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
++{
++ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
++
++ intel_dp->as_sdp_supported = HAS_AS_SDP(i915) &&
++ drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
++}
++
+ static int
+ intel_dp_detect(struct drm_connector *connector,
+ struct drm_modeset_acquire_ctx *ctx,
+@@ -5991,6 +5991,8 @@ intel_dp_detect(struct drm_connector *co
+
+ intel_dp_detect_dsc_caps(intel_dp, intel_connector);
+
++ intel_dp_detect_sdp_caps(intel_dp);
++
+ intel_dp_mst_configure(intel_dp);
+
+ if (intel_dp->reset_link_params) {
+--- a/drivers/gpu/drm/i915/display/intel_dp.h
++++ b/drivers/gpu/drm/i915/display/intel_dp.h
+@@ -85,7 +85,6 @@ void intel_dp_audio_compute_config(struc
+ struct drm_connector_state *conn_state);
+ bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp);
+ bool intel_dp_is_edp(struct intel_dp *intel_dp);
+-bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp);
+ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
+ bool intel_dp_has_dsc(const struct intel_connector *connector);
+ int intel_dp_link_symbol_size(int rate);
+--- a/drivers/gpu/drm/i915/display/intel_vrr.c
++++ b/drivers/gpu/drm/i915/display/intel_vrr.c
+@@ -233,8 +233,7 @@ intel_vrr_compute_config(struct intel_cr
+ crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+ }
+
+- if (intel_dp_as_sdp_supported(intel_dp) &&
+- crtc_state->vrr.enable) {
++ if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) {
+ crtc_state->vrr.vsync_start =
+ (crtc_state->hw.adjusted_mode.crtc_vtotal -
+ crtc_state->hw.adjusted_mode.vsync_start);
--- /dev/null
+From stable+bounces-87993-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:31 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:05 -0700
+Subject: drm/i915/display: Don't enable decompression on Xe2 with Tile4
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>, Mika Kahola <mika.kahola@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-13-lucas.demarchi@intel.com>
+
+From: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
+
+commit 4cce34b3835b6f7dc52ee2da95c96b6364bb72e5 upstream.
+
+>>From now on expect Tile4 not to be using compression
+
+Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
+Reviewed-by: Mika Kahola <mika.kahola@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240816115229.531671-2-juhapekka.heikkila@gmail.com
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
++++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
+@@ -1085,11 +1085,6 @@ static u32 skl_plane_ctl(const struct in
+ if (DISPLAY_VER(dev_priv) == 13)
+ plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
+
+- if (GRAPHICS_VER(dev_priv) >= 20 &&
+- fb->modifier == I915_FORMAT_MOD_4_TILED) {
+- plane_ctl |= PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+- }
+-
+ return plane_ctl;
+ }
+
--- /dev/null
+From stable+bounces-87988-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:12 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:00 -0700
+Subject: drm/i915/display/dp: Compute AS SDP when vrr is also enabled
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>, Arun R Murthy <arun.r.murthy@intel.com>, Jani Nikula <jani.nikula@linux.intel.com>, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Ankit Nautiyal <ankit.k.nautiyal@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-8-lucas.demarchi@intel.com>
+
+From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+
+commit eb53e5b933b9ff315087305b3dc931af3067d19c upstream.
+
+AS SDP should be computed when VRR timing generator is also enabled.
+Correct the compute condition to compute params of Adaptive sync SDP
+when VRR timing genrator is enabled along with sink support indication.
+
+--v2:
+Modify if condition (Jani).
+
+Fixes: b2013783c445 ("drm/i915/display: Cache adpative sync caps to use it later")
+Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+Cc: Arun R Murthy <arun.r.murthy@intel.com>
+Cc: Jani Nikula <jani.nikula@linux.intel.com>
+Cc: intel-gfx@lists.freedesktop.org
+Cc: intel-xe@lists.freedesktop.org
+Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+(added prefix drm in subject)
+Link: https://patchwork.freedesktop.org/patch/msgid/20240730040941.396862-1-mitulkumar.ajitkumar.golani@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_dp.c
++++ b/drivers/gpu/drm/i915/display/intel_dp.c
+@@ -2627,7 +2627,7 @@ static void intel_dp_compute_as_sdp(stru
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+
+- if (!crtc_state->vrr.enable || intel_dp->as_sdp_supported)
++ if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
+ return;
+
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
--- /dev/null
+From stable+bounces-87984-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:05 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:37:56 -0700
+Subject: drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>, Nemesa Garg <nemesa.garg@intel.com>, Suraj Kandpal <suraj.kandpal@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-4-lucas.demarchi@intel.com>
+
+From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+
+commit 7fbad577c82c5dd6db7217855c26f51554e53d85 upstream.
+
+The dispcnlunit1_cp_xosc_clk should be de-asserted in display off
+and only asserted in display on. As part of this workaround, Display
+driver shall execute set-reset sequence at the end of the initialize
+sequence to ensure clk does not remain active in display OFF.
+
+--v2:
+- Rebase.
+--v3:
+- Correct HSD number in commit message.
+--v4:
+- Reformat commit message.
+- Use intel_de_rmw instead of intel_de_write
+--v5:
+- Build Fixes.
+
+WA: 15013987218
+Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
+Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
+Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
+Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240708083247.2611258-1-mitulkumar.ajitkumar.golani@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/i915/display/intel_display_power.c
++++ b/drivers/gpu/drm/i915/display/intel_display_power.c
+@@ -1704,6 +1704,14 @@ static void icl_display_core_init(struct
+ /* Wa_14011503030:xelpd */
+ if (DISPLAY_VER(dev_priv) == 13)
+ intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
++
++ /* Wa_15013987218 */
++ if (DISPLAY_VER(dev_priv) == 20) {
++ intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
++ 0, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE);
++ intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
++ PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 0);
++ }
+ }
+
+ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
--- /dev/null
+From stable+bounces-87987-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:07 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:37:59 -0700
+Subject: drm/i915/dp: Clear VSC SDP during post ddi disable routine
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Suraj Kandpal <suraj.kandpal@intel.com>, Ankit Nautiyal <ankit.k.nautiyal@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-7-lucas.demarchi@intel.com>
+
+From: Suraj Kandpal <suraj.kandpal@intel.com>
+
+commit 3e307d6c28e7bc7d94b5699d0ed7fe07df6db094 upstream.
+
+Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable
+routine i.e with the variable of enable as false. This is to avoid
+an infoframes.enable mismatch issue which is caused when pipe is
+connected to eDp which has psr then connected to DPMST. In this case
+eDp's post ddi disable routine does not clear infoframes.enable VSC
+for the given pipe and DPMST does not recompute VSC SDP and write
+infoframes.enable which causes a mismatch.
+
+--v2
+-Make the comment match the code [Jani]
+
+Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240724163743.3668407-1-suraj.kandpal@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_dp.c
++++ b/drivers/gpu/drm/i915/display/intel_dp.c
+@@ -4393,8 +4393,11 @@ void intel_dp_set_infoframes(struct inte
+ if (!enable && HAS_DSC(dev_priv))
+ val &= ~VDIP_ENABLE_PPS;
+
+- /* When PSR is enabled, this routine doesn't disable VSC DIP */
+- if (!crtc_state->has_psr)
++ /*
++ * This routine disables VSC DIP if the function is called
++ * to disable SDP or if it does not have PSR
++ */
++ if (!enable || !crtc_state->has_psr)
+ val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
+
+ intel_de_write(dev_priv, reg, val);
--- /dev/null
+From stable+bounces-87986-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:07 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:37:58 -0700
+Subject: drm/i915/hdcp: Add encoder check in hdcp2_get_capability
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Suraj Kandpal <suraj.kandpal@intel.com>, Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-6-lucas.demarchi@intel.com>
+
+From: Suraj Kandpal <suraj.kandpal@intel.com>
+
+commit d34f4f058edf1235c103ca9c921dc54820d14d40 upstream.
+
+Add encoder check in intel_hdcp2_get_capability to avoid
+null pointer error.
+
+Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240722064451.3610512-3-suraj.kandpal@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
++++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+@@ -677,8 +677,15 @@ static
+ int intel_dp_hdcp2_get_capability(struct intel_connector *connector,
+ bool *capable)
+ {
+- struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+- struct drm_dp_aux *aux = &dig_port->dp.aux;
++ struct intel_digital_port *dig_port;
++ struct drm_dp_aux *aux;
++
++ *capable = false;
++ if (!intel_attached_encoder(connector))
++ return -EINVAL;
++
++ dig_port = intel_attached_dig_port(connector);
++ aux = &dig_port->dp.aux;
+
+ return _intel_dp_hdcp2_get_capability(aux, capable);
+ }
--- /dev/null
+From stable+bounces-87985-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:06 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:37:57 -0700
+Subject: drm/i915/hdcp: Add encoder check in intel_hdcp_get_capability
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Suraj Kandpal <suraj.kandpal@intel.com>, Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-5-lucas.demarchi@intel.com>
+
+From: Suraj Kandpal <suraj.kandpal@intel.com>
+
+commit 31b42af516afa1e184d1a9f9dd4096c54044269a upstream.
+
+Sometimes during hotplug scenario or suspend/resume scenario encoder is
+not always initialized when intel_hdcp_get_capability add
+a check to avoid kernel null pointer dereference.
+
+Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240722064451.3610512-2-suraj.kandpal@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_hdcp.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
++++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
+@@ -203,11 +203,16 @@ int intel_hdcp_read_valid_bksv(struct in
+ /* Is HDCP1.4 capable on Platform and Sink */
+ bool intel_hdcp_get_capability(struct intel_connector *connector)
+ {
+- struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
++ struct intel_digital_port *dig_port;
+ const struct intel_hdcp_shim *shim = connector->hdcp.shim;
+ bool capable = false;
+ u8 bksv[5];
+
++ if (!intel_attached_encoder(connector))
++ return capable;
++
++ dig_port = intel_attached_dig_port(connector);
++
+ if (!shim)
+ return capable;
+
--- /dev/null
+From stable+bounces-87991-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:27 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:02 -0700
+Subject: drm/i915: move rawclk from runtime to display runtime info
+To: stable@vger.kernel.org
+Cc: "Rodrigo Vivi" <rodrigo.vivi@intel.com>, "Jani Nikula" <jani.nikula@intel.com>, "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>, "Ville Syrjälä" <ville.syrjala@linux.intel.com>, "Lucas De Marchi" <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-10-lucas.demarchi@intel.com>
+
+From: Jani Nikula <jani.nikula@intel.com>
+
+commit a9556637a23311dea96f27fa3c3e5bfba0b38ae4 upstream.
+
+It's mostly about display, so move it under display. This should also
+fix rawclk freq initialization in the xe driver.
+
+v2: Change the init location
+
+Link: https://lore.kernel.org/r/20240819133138.147511-2-maarten.lankhorst@linux.intel.com
+Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/39330d09c48509e013f01fd0247a9b7c291173e2.1724144570.git.jani.nikula@intel.com
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_backlight.c | 10 +++++-----
+ drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++
+ drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++
+ drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
+ drivers/gpu/drm/i915/display/intel_dp_aux.c | 4 ++--
+ drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
+ drivers/gpu/drm/i915/intel_device_info.c | 5 -----
+ drivers/gpu/drm/i915/intel_device_info.h | 2 --
+ 8 files changed, 17 insertions(+), 17 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_backlight.c
++++ b/drivers/gpu/drm/i915/display/intel_backlight.c
+@@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_co
+ {
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
+- return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
++ return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
+ pwm_freq_hz);
+ }
+
+@@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_co
+ {
+ struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
+- return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
++ return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
+ pwm_freq_hz * 128);
+ }
+
+@@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_c
+ int clock;
+
+ if (IS_PINEVIEW(i915))
+- clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
++ clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
+ else
+ clock = KHz(i915->display.cdclk.hw.cdclk);
+
+@@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_c
+ int clock;
+
+ if (IS_G4X(i915))
+- clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
++ clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
+ else
+ clock = KHz(i915->display.cdclk.hw.cdclk);
+
+@@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_co
+ clock = MHz(25);
+ mul = 16;
+ } else {
+- clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
++ clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
+ mul = 128;
+ }
+
+--- a/drivers/gpu/drm/i915/display/intel_display_device.c
++++ b/drivers/gpu/drm/i915/display/intel_display_device.c
+@@ -1474,6 +1474,9 @@ static void __intel_display_device_info_
+ }
+ }
+
++ display_runtime->rawclk_freq = intel_read_rawclk(i915);
++ drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);
++
+ return;
+
+ display_fused_off:
+@@ -1516,6 +1519,8 @@ void intel_display_device_info_print(con
+ drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
+ drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
+ drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
++
++ drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
+ }
+
+ /*
+--- a/drivers/gpu/drm/i915/display/intel_display_device.h
++++ b/drivers/gpu/drm/i915/display/intel_display_device.h
+@@ -204,6 +204,8 @@ struct intel_display_runtime_info {
+ u16 step;
+ } ip;
+
++ u32 rawclk_freq;
++
+ u8 pipe_mask;
+ u8 cpu_transcoder_mask;
+ u16 port_mask;
+--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
++++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
+@@ -1176,9 +1176,9 @@ static void vlv_init_display_clock_gatin
+ MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+ intel_de_write(dev_priv, CBR1_VLV, 0);
+
+- drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
++ drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
+ intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
+- DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
++ DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq,
+ 1000));
+ }
+
+--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
++++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
+@@ -84,7 +84,7 @@ static u32 g4x_get_aux_clock_divider(str
+ * The clock divider is based off the hrawclk, and would like to run at
+ * 2MHz. So, take the hrawclk value and divide by 2000 and use that
+ */
+- return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000);
++ return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq, 2000);
+ }
+
+ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
+@@ -104,7 +104,7 @@ static u32 ilk_get_aux_clock_divider(str
+ if (dig_port->aux_ch == AUX_CH_A)
+ freq = i915->display.cdclk.hw.cdclk;
+ else
+- freq = RUNTIME_INFO(i915)->rawclk_freq;
++ freq = DISPLAY_RUNTIME_INFO(i915)->rawclk_freq;
+ return DIV_ROUND_CLOSEST(freq, 2000);
+ }
+
+--- a/drivers/gpu/drm/i915/display/intel_pps.c
++++ b/drivers/gpu/drm/i915/display/intel_pps.c
+@@ -1483,7 +1483,7 @@ static void pps_init_registers(struct in
+ {
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u32 pp_on, pp_off, port_sel = 0;
+- int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
++ int div = DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
+ struct pps_registers regs;
+ enum port port = dp_to_dig_port(intel_dp)->base.port;
+ const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
+--- a/drivers/gpu/drm/i915/intel_device_info.c
++++ b/drivers/gpu/drm/i915/intel_device_info.c
+@@ -124,7 +124,6 @@ void intel_device_info_print(const struc
+ #undef PRINT_FLAG
+
+ drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
+- drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
+ }
+
+ #define ID(id) (id)
+@@ -377,10 +376,6 @@ void intel_device_info_runtime_init(stru
+ "Disabling ppGTT for VT-d support\n");
+ runtime->ppgtt_type = INTEL_PPGTT_NONE;
+ }
+-
+- runtime->rawclk_freq = intel_read_rawclk(dev_priv);
+- drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
+-
+ }
+
+ /*
+--- a/drivers/gpu/drm/i915/intel_device_info.h
++++ b/drivers/gpu/drm/i915/intel_device_info.h
+@@ -207,8 +207,6 @@ struct intel_runtime_info {
+
+ u16 device_id;
+
+- u32 rawclk_freq;
+-
+ struct intel_step_info step;
+
+ unsigned int page_sizes; /* page sizes supported by the HW */
--- /dev/null
+From stable+bounces-87989-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:21 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:01 -0700
+Subject: drm/i915/pps: Disable DPLS_GATING around pps sequence
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Suraj Kandpal <suraj.kandpal@intel.com>, Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-9-lucas.demarchi@intel.com>
+
+From: Suraj Kandpal <suraj.kandpal@intel.com>
+
+commit c7085d08c7e53d9aef0cdd4b20798356f6f5d469 upstream.
+
+Disable bit 29 of SCLKGATE_DIS register around pps sequence
+when we turn panel power on.
+
+--v2
+-Squash two commit together [Jani]
+-Use IS_DISPLAY_VER [Jani]
+-Fix multiline comment [Jani]
+
+--v3
+-Define register in a more appropriate place [Mitul]
+
+--v4
+-Register is already defined no need to define it again [Ville]
+-Use correct WA number (lineage no.) [Dnyaneshwar]
+-Fix the range on which this WA is applied [Dnyaneshwar]
+
+Bspec: 49304
+Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240813042807.4015214-1-suraj.kandpal@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_pps.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/i915/display/intel_pps.c
++++ b/drivers/gpu/drm/i915/display/intel_pps.c
+@@ -951,6 +951,14 @@ void intel_pps_on_unlocked(struct intel_
+ intel_de_posting_read(dev_priv, pp_ctrl_reg);
+ }
+
++ /*
++ * WA: 22019252566
++ * Disable DPLS gating around power sequence.
++ */
++ if (IS_DISPLAY_VER(dev_priv, 13, 14))
++ intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
++ 0, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
++
+ pp |= PANEL_POWER_ON;
+ if (!IS_IRONLAKE(dev_priv))
+ pp |= PANEL_POWER_RESET;
+@@ -961,6 +969,10 @@ void intel_pps_on_unlocked(struct intel_
+ wait_panel_on(intel_dp);
+ intel_dp->pps.last_power_on = jiffies;
+
++ if (IS_DISPLAY_VER(dev_priv, 13, 14))
++ intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D,
++ PCH_DPLSUNIT_CLOCK_GATE_DISABLE, 0);
++
+ if (IS_IRONLAKE(dev_priv)) {
+ pp |= PANEL_POWER_RESET; /* restore panel reset bit */
+ intel_de_write(dev_priv, pp_ctrl_reg, pp);
--- /dev/null
+From stable+bounces-87992-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:30 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:04 -0700
+Subject: drm/i915/psr: Prevent Panel Replay if CRC calculation is enabled
+To: stable@vger.kernel.org
+Cc: "Rodrigo Vivi" <rodrigo.vivi@intel.com>, "Jouni Högander" <jouni.hogander@intel.com>, "Mika Kahola" <mika.kahola@intel.com>, "Lucas De Marchi" <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-12-lucas.demarchi@intel.com>
+
+From: Jouni Högander <jouni.hogander@intel.com>
+
+commit a8efd8ce280996fe29f2564f705e96e18da3fa62 upstream.
+
+Similarly as for PSR2 CRC calculation seems to timeout when Panel Replay is
+enabled. Fix this by falling back to PSR if CRC calculation is enabled.
+
+Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2266
+Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
+Reviewed-by: Mika Kahola <mika.kahola@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240819092549.1298233-1-jouni.hogander@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/gpu/drm/i915/display/intel_psr.c
++++ b/drivers/gpu/drm/i915/display/intel_psr.c
+@@ -1605,6 +1605,12 @@ _panel_replay_compute_config(struct inte
+ if (!alpm_config_valid(intel_dp, crtc_state, true))
+ return false;
+
++ if (crtc_state->crc_enabled) {
++ drm_dbg_kms(&i915->drm,
++ "Panel Replay not enabled because it would inhibit pipe CRC calculation\n");
++ return false;
++ }
++
+ return true;
+ }
+
--- /dev/null
+From stable+bounces-87981-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:03 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:37:53 -0700
+Subject: drm/i915: Skip programming FIA link enable bits for MTL+
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Gustavo Sousa <gustavo.sousa@intel.com>, Shekhar Chauhan <shekhar.chauhan@intel.com>, Imre Deak <imre.deak@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-1-lucas.demarchi@intel.com>
+
+From: Gustavo Sousa <gustavo.sousa@intel.com>
+
+commit 9fc97277eb2d17492de636b68cf7d2f5c4f15c1b upstream.
+
+Starting with Xe_LPD+, although FIA is still used to readout Type-C pin
+assignment, part of Type-C support is moved to PICA and programming
+PORT_TX_DFLEXDPMLE1(*) registers is not applicable anymore like it was
+for previous display IPs (e.g. see BSpec 49190).
+
+v2:
+ - Mention Bspec 49190 as a reference of instructions for previous
+ IPs. (Shekhar Chauhan)
+ - s/Xe_LPDP/Xe_LPD+/ in the commit message. (Matt Roper)
+ - Update commit message to be more accurate to the changes in the IP.
+ (Imre Deak)
+
+Bspec: 65750, 65448
+Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
+Reviewed-by: Imre Deak <imre.deak@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240625202652.315936-1-gustavo.sousa@intel.com
+Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_tc.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/i915/display/intel_tc.c
++++ b/drivers/gpu/drm/i915/display/intel_tc.c
+@@ -393,6 +393,9 @@ void intel_tc_port_set_fia_lane_count(st
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+ u32 val;
+
++ if (DISPLAY_VER(i915) >= 14)
++ return;
++
+ drm_WARN_ON(&i915->drm,
+ lane_reversal && tc->mode != TC_PORT_LEGACY);
+
--- /dev/null
+From stable+bounces-87999-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:54 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:13 -0700
+Subject: drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Tejas Upadhyay <tejas.upadhyay@intel.com>, Shekhar Chauhan <shekhar.chauhan@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-21-lucas.demarchi@intel.com>
+
+From: Tejas Upadhyay <tejas.upadhyay@intel.com>
+
+commit 4551d60299b5ddc2655b6b365a4b92634e14e04f upstream.
+
+Register STATELESS_COMPRESSION_CTRL should be considered
+mcr register which should write to all slices as per
+documentation.
+
+Bspec: 71185
+Fixes: ecabb5e6ce54 ("drm/xe/xe2: Add performance turning changes")
+Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
+Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240814095614.909774-4-tejas.upadhyay@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
++++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+@@ -80,7 +80,7 @@
+ #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
+ #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
+
+-#define STATELESS_COMPRESSION_CTRL XE_REG(0x4148)
++#define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148)
+ #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0)
+
+ #define XE2_GAMREQSTRM_CTRL XE_REG(0x4194)
--- /dev/null
+From stable+bounces-87990-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:22 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:03 -0700
+Subject: drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO()
+To: stable@vger.kernel.org
+Cc: "Rodrigo Vivi" <rodrigo.vivi@intel.com>, "Jani Nikula" <jani.nikula@intel.com>, "Ville Syrjälä" <ville.syrjala@linux.intel.com>, "Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>, "Lucas De Marchi" <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-11-lucas.demarchi@intel.com>
+
+From: Jani Nikula <jani.nikula@intel.com>
+
+commit f15e5587448989a55cf8b4feaad0df72ca3aa6a0 upstream.
+
+With rawclk_freq moved to display runtime info, xe has no users left for
+them.
+
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/9f09274bddc14f555c0102f37af6df23b4433102.1724144570.git.jani.nikula@intel.com
+Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 -
+ drivers/gpu/drm/xe/xe_device_types.h | 6 ------
+ 2 files changed, 7 deletions(-)
+
+--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
++++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+@@ -116,7 +116,6 @@ struct i915_sched_attr {
+ #define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0)
+
+ #define pdev_to_i915 pdev_to_xe_device
+-#define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime)
+
+ #define FORCEWAKE_ALL XE_FORCEWAKE_ALL
+
+--- a/drivers/gpu/drm/xe/xe_device_types.h
++++ b/drivers/gpu/drm/xe/xe_device_types.h
+@@ -297,12 +297,6 @@ struct xe_device {
+ u8 has_atomic_enable_pte_bit:1;
+ /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */
+ u8 has_device_atomics_on_smem:1;
+-
+-#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
+- struct {
+- u32 rawclk_freq;
+- } i915_runtime;
+-#endif
+ } info;
+
+ /** @irq: device interrupt state */
--- /dev/null
+From stable+bounces-87996-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:43 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:09 -0700
+Subject: drm/xe: Move enable host l2 VRAM post MCR init
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Tejas Upadhyay <tejas.upadhyay@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>, Matt Roper <matthew.d.roper@intel.com>
+Message-ID: <20241024033815.3538736-17-lucas.demarchi@intel.com>
+
+From: Tejas Upadhyay <tejas.upadhyay@intel.com>
+
+commit ab0d6ef864c5fa820e894ee1a07f861e63851664 upstream.
+
+xe_gt_enable_host_l2_vram() is reading the XE2_GAMREQSTRM_CTRL register
+that is currently missing the MCR annotation. However, just adding the
+annotation doesn't work as this function is called before MCR handling
+is initialized in xe_gt_mcr_init().
+
+xe_gt_enable_host_l2_vram() is used to implement WA 16023588340 that
+needs to be done as early as possible during initialization in order to
+be effective since the MMIO writes impact it. In the failure scenario,
+driver would simply not be able to bind successfully.
+
+Moving xe_gt_enable_host_l2_vram() later, after MCR initialization is
+done, only incurs a few additional HW accesses, particularly when
+loading GuC for hwconfig. Binding/unbinding the driver 100 times in BMG
+still works so it should be ok to start handling the WA a little bit
+later. This is sufficient to allow adding the MCR annotation to
+XE2_GAMREQSTRM_CTRL.
+
+Cc: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
+Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
+Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240814095614.909774-2-tejas.upadhyay@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/xe_gt.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/xe/xe_gt.c
++++ b/drivers/gpu/drm/xe/xe_gt.c
+@@ -555,7 +555,6 @@ int xe_gt_init_hwconfig(struct xe_gt *gt
+
+ xe_gt_mcr_init_early(gt);
+ xe_pat_init(gt);
+- xe_gt_enable_host_l2_vram(gt);
+
+ err = xe_uc_init(>->uc);
+ if (err)
+@@ -567,6 +566,7 @@ int xe_gt_init_hwconfig(struct xe_gt *gt
+
+ xe_gt_topology_init(gt);
+ xe_gt_mcr_init(gt);
++ xe_gt_enable_host_l2_vram(gt);
+
+ out_fw:
+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
--- /dev/null
+From stable+bounces-87994-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:36 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:06 -0700
+Subject: drm/xe: Support 'nomodeset' kernel command-line option
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Thomas Zimmermann <tzimmermann@suse.de>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-14-lucas.demarchi@intel.com>
+
+From: Thomas Zimmermann <tzimmermann@suse.de>
+
+commit 014125c64d09e58e90dde49fbb57d802a13e2559 upstream.
+
+Setting 'nomodeset' on the kernel command line disables all graphics
+drivers with modesetting capabilities, leaving only firmware drivers,
+such as simpledrm or efifb.
+
+Most DRM drivers automatically support 'nomodeset' via DRM's module
+helper macros. In xe, which uses regular module_init(), manually call
+drm_firmware_drivers_only() to test for 'nomodeset'. Do not register
+the driver if set.
+
+v2:
+- use xe's init table (Lucas)
+- do NULL test for init/exit functions
+
+Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
+Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240827121003.97429-1-tzimmermann@suse.de
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/xe_module.c | 39 ++++++++++++++++++++++++++++++++++++---
+ 1 file changed, 36 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/xe/xe_module.c
++++ b/drivers/gpu/drm/xe/xe_module.c
+@@ -8,6 +8,8 @@
+ #include <linux/init.h>
+ #include <linux/module.h>
+
++#include <drm/drm_module.h>
++
+ #include "xe_drv.h"
+ #include "xe_hw_fence.h"
+ #include "xe_pci.h"
+@@ -61,6 +63,14 @@ module_param_named_unsafe(wedged_mode, x
+ MODULE_PARM_DESC(wedged_mode,
+ "Module's default policy for the wedged mode - 0=never, 1=upon-critical-errors[default], 2=upon-any-hang");
+
++static int xe_check_nomodeset(void)
++{
++ if (drm_firmware_drivers_only())
++ return -ENODEV;
++
++ return 0;
++}
++
+ struct init_funcs {
+ int (*init)(void);
+ void (*exit)(void);
+@@ -68,6 +78,9 @@ struct init_funcs {
+
+ static const struct init_funcs init_funcs[] = {
+ {
++ .init = xe_check_nomodeset,
++ },
++ {
+ .init = xe_hw_fence_module_init,
+ .exit = xe_hw_fence_module_exit,
+ },
+@@ -85,15 +98,35 @@ static const struct init_funcs init_func
+ },
+ };
+
++static int __init xe_call_init_func(unsigned int i)
++{
++ if (WARN_ON(i >= ARRAY_SIZE(init_funcs)))
++ return 0;
++ if (!init_funcs[i].init)
++ return 0;
++
++ return init_funcs[i].init();
++}
++
++static void xe_call_exit_func(unsigned int i)
++{
++ if (WARN_ON(i >= ARRAY_SIZE(init_funcs)))
++ return;
++ if (!init_funcs[i].exit)
++ return;
++
++ init_funcs[i].exit();
++}
++
+ static int __init xe_init(void)
+ {
+ int err, i;
+
+ for (i = 0; i < ARRAY_SIZE(init_funcs); i++) {
+- err = init_funcs[i].init();
++ err = xe_call_init_func(i);
+ if (err) {
+ while (i--)
+- init_funcs[i].exit();
++ xe_call_exit_func(i);
+ return err;
+ }
+ }
+@@ -106,7 +139,7 @@ static void __exit xe_exit(void)
+ int i;
+
+ for (i = ARRAY_SIZE(init_funcs) - 1; i >= 0; i--)
+- init_funcs[i].exit();
++ xe_call_exit_func(i);
+ }
+
+ module_init(xe_init);
--- /dev/null
+From stable+bounces-88000-greg=kroah.com@vger.kernel.org Thu Oct 24 05:40:07 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:14 -0700
+Subject: drm/xe: Write all slices if its mcr register
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Tejas Upadhyay <tejas.upadhyay@intel.com>, Matt Roper <matthew.d.roper@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-22-lucas.demarchi@intel.com>
+
+From: Tejas Upadhyay <tejas.upadhyay@intel.com>
+
+commit f0ffa657e9f3913c7921cbd4d876343401f15f52 upstream.
+
+Register GAMREQSTRM_CTRL should be considered mcr register
+which should write to all slices as per documentation.
+
+Bspec: 71185
+Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
+Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
+Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240814095614.909774-3-tejas.upadhyay@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
+ drivers/gpu/drm/xe/xe_gt.c | 8 ++++----
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
++++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+@@ -83,7 +83,7 @@
+ #define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148)
+ #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0)
+
+-#define XE2_GAMREQSTRM_CTRL XE_REG(0x4194)
++#define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194)
+ #define CG_DIS_CNTLBUS REG_BIT(6)
+
+ #define CCS_AUX_INV XE_REG(0x4208)
+--- a/drivers/gpu/drm/xe/xe_gt.c
++++ b/drivers/gpu/drm/xe/xe_gt.c
+@@ -109,9 +109,9 @@ static void xe_gt_enable_host_l2_vram(st
+
+ if (!xe_gt_is_media_type(gt)) {
+ xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
+- reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
++ reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
+ reg |= CG_DIS_CNTLBUS;
+- xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
++ xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
+ }
+
+ xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3);
+@@ -133,9 +133,9 @@ static void xe_gt_disable_host_l2_vram(s
+ if (WARN_ON(err))
+ return;
+
+- reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
++ reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
+ reg &= ~CG_DIS_CNTLBUS;
+- xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
++ xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
+
+ xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
+ }
--- /dev/null
+From stable+bounces-87998-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:52 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:12 -0700
+Subject: drm/xe/xe2: Add performance turning changes
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Shekhar Chauhan <shekhar.chauhan@intel.com>, Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>, Akshata Jahagirdar <akshata.jahagirdar@intel.com>, Matt Roper <matthew.d.roper@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-20-lucas.demarchi@intel.com>
+
+From: Shekhar Chauhan <shekhar.chauhan@intel.com>
+
+commit ecabb5e6ce54711c28706fc794d77adb3ecd0605 upstream.
+
+Update performance tuning according to the hardware spec.
+
+Bspec: 72161
+Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
+Reviewed-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
+Reviewed-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
+Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240805053710.877119-1-shekhar.chauhan@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 ++++
+ drivers/gpu/drm/xe/xe_tuning.c | 8 +++++++-
+ 2 files changed, 11 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
++++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+@@ -80,6 +80,9 @@
+ #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
+ #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
+
++#define STATELESS_COMPRESSION_CTRL XE_REG(0x4148)
++#define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0)
++
+ #define XE2_GAMREQSTRM_CTRL XE_REG(0x4194)
+ #define CG_DIS_CNTLBUS REG_BIT(6)
+
+@@ -194,6 +197,7 @@
+ #define GSCPSMI_BASE XE_REG(0x880c)
+
+ #define CCCHKNREG1 XE_REG_MCR(0x8828)
++#define L3CMPCTRL REG_BIT(23)
+ #define ENCOMPPERFFIX REG_BIT(18)
+
+ /* Fuse readout registers for GT */
+--- a/drivers/gpu/drm/xe/xe_tuning.c
++++ b/drivers/gpu/drm/xe/xe_tuning.c
+@@ -39,7 +39,8 @@ static const struct xe_rtp_entry_sr gt_t
+ },
+ { XE_RTP_NAME("Tuning: Compression Overfetch"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+- XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX)),
++ XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
++ SET(CCCHKNREG1, L3CMPCTRL))
+ },
+ { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+@@ -50,6 +51,11 @@ static const struct xe_rtp_entry_sr gt_t
+ XE_RTP_ACTIONS(SET(L3SQCREG2,
+ COMPMEMRD256BOVRFETCHEN))
+ },
++ { XE_RTP_NAME("Tuning: Stateless compression control"),
++ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
++ XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT,
++ REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0)))
++ },
+ {}
+ };
+
--- /dev/null
+From stable+bounces-88002-greg=kroah.com@vger.kernel.org Thu Oct 24 05:40:11 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:11 -0700
+Subject: drm/xe/xe2: Introduce performance changes
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Akshata Jahagirdar <akshata.jahagirdar@intel.com>, Matt Roper <matthew.d.roper@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-19-lucas.demarchi@intel.com>
+
+From: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
+
+commit 2009e808bc3e0df6d4d83e2271bc25ae63a4ac05 upstream.
+
+Add Compression Performance Improvement Changes in Xe2
+
+v2: Rebase
+
+v3: Rebase, updated as per latest changes on bspec,
+ Removed unnecessary default actions (Matt)
+ formatting nits (Tejas)
+
+v4: Formatting nits, removed default set action for bit 14 (Matt)
+
+Bspec: 72161
+Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com>
+Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
+Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/c2dd753fdc55df6a6432026f2df9c2684a0d25c1.1722607628.git.akshata.jahagirdar@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
+ drivers/gpu/drm/xe/xe_tuning.c | 5 +++++
+ 2 files changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
++++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+@@ -368,6 +368,9 @@
+ #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
+ #define XEHP_LNESPARE REG_BIT(19)
+
++#define L3SQCREG2 XE_REG_MCR(0xb104)
++#define COMPMEMRD256BOVRFETCHEN REG_BIT(20)
++
+ #define L3SQCREG3 XE_REG_MCR(0xb108)
+ #define COMPPWOVERFETCHEN REG_BIT(28)
+
+--- a/drivers/gpu/drm/xe/xe_tuning.c
++++ b/drivers/gpu/drm/xe/xe_tuning.c
+@@ -45,6 +45,11 @@ static const struct xe_rtp_entry_sr gt_t
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+ XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
+ },
++ { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
++ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
++ XE_RTP_ACTIONS(SET(L3SQCREG2,
++ COMPMEMRD256BOVRFETCHEN))
++ },
+ {}
+ };
+
--- /dev/null
+From stable+bounces-88001-greg=kroah.com@vger.kernel.org Thu Oct 24 05:40:07 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:07 -0700
+Subject: drm/xe/xe2hpg: Add Wa_15016589081
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Tejas Upadhyay <tejas.upadhyay@intel.com>, Gustavo Sousa <gustavo.sousa@intel.com>, Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>, Nirmoy Das <nirmoy.das@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-15-lucas.demarchi@intel.com>
+
+From: Tejas Upadhyay <tejas.upadhyay@intel.com>
+
+commit da9a73b7b25eab574cb9c984fcce0b5e240bdd2c upstream.
+
+Wa_15016589081 applies to xe2_hpg renderCS
+
+V2(Gustavo)
+ - rename bit macro
+
+Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
+Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
+Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240904101333.2049655-1-tejas.upadhyay@intel.com
+Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
+(cherry picked from commit 9db969b36b2fbca13ad4088aff725ebd5e8142f5)
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 +
+ drivers/gpu/drm/xe/xe_wa.c | 4 ++++
+ 2 files changed, 5 insertions(+)
+
+--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
++++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+@@ -102,6 +102,7 @@
+
+ #define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
+ #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8)
++#define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6)
+
+ #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
+ #define TBIMR_FAST_CLIP REG_BIT(5)
+--- a/drivers/gpu/drm/xe/xe_wa.c
++++ b/drivers/gpu/drm/xe/xe_wa.c
+@@ -733,6 +733,10 @@ static const struct xe_rtp_entry_sr lrc_
+ DIS_PARTIAL_AUTOSTRIP |
+ DIS_AUTOSTRIP))
+ },
++ { XE_RTP_NAME("15016589081"),
++ XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
++ XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
++ },
+
+ {}
+ };
--- /dev/null
+From stable+bounces-87997-greg=kroah.com@vger.kernel.org Thu Oct 24 05:39:48 2024
+From: Lucas De Marchi <lucas.demarchi@intel.com>
+Date: Wed, 23 Oct 2024 20:38:10 -0700
+Subject: drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPG
+To: stable@vger.kernel.org
+Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>, Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>, Gustavo Sousa <gustavo.sousa@intel.com>, Matt Roper <matthew.d.roper@intel.com>, Lucas De Marchi <lucas.demarchi@intel.com>
+Message-ID: <20241024033815.3538736-18-lucas.demarchi@intel.com>
+
+From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
+
+commit e4ac526c440af8aa94d2bdfe6066339dd93b4db2 upstream.
+
+Add performance tuning changes for Xe2_HPG
+
+Bspec: 72161
+Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
+Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
+Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240724121521.2347524-1-sai.teja.pottumuttu@intel.com
+Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 +
+ drivers/gpu/drm/xe/xe_tuning.c | 8 ++++++++
+ 2 files changed, 9 insertions(+)
+
+--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
++++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+@@ -109,6 +109,7 @@
+
+ #define FF_MODE XE_REG_MCR(0x6210)
+ #define DIS_TE_AUTOSTRIP REG_BIT(31)
++#define VS_HIT_MAX_VALUE_MASK REG_GENMASK(25, 20)
+ #define DIS_MESH_PARTIAL_AUTOSTRIP REG_BIT(16)
+ #define DIS_MESH_AUTOSTRIP REG_BIT(15)
+
+--- a/drivers/gpu/drm/xe/xe_tuning.c
++++ b/drivers/gpu/drm/xe/xe_tuning.c
+@@ -93,6 +93,14 @@ static const struct xe_rtp_entry_sr lrc_
+ REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
+ },
+
++ /* Xe2_HPG */
++
++ { XE_RTP_NAME("Tuning: vs hit max value"),
++ XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
++ XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
++ REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
++ },
++
+ {}
+ };
+
arm64-dts-imx8ulp-correct-the-flexspi-compatible-string.patch
arm64-dts-qcom-x1e80100-add-broadcast_and-region-in-llcc-block.patch
arm64-dts-qcom-x1e80100-fix-pcie4-and-pcie6a-phy-clocks.patch
+drm-i915-skip-programming-fia-link-enable-bits-for-mtl.patch
+drm-i915-disable-fbc-due-to-wa_16023588340.patch
+drm-i915-display-cache-adpative-sync-caps-to-use-it-later.patch
+drm-i915-display-wa-for-re-initialize-dispcnlunitt1-xosc-clock.patch
+drm-i915-hdcp-add-encoder-check-in-intel_hdcp_get_capability.patch
+drm-i915-hdcp-add-encoder-check-in-hdcp2_get_capability.patch
+drm-i915-dp-clear-vsc-sdp-during-post-ddi-disable-routine.patch
+drm-i915-display-dp-compute-as-sdp-when-vrr-is-also-enabled.patch
+drm-i915-pps-disable-dpls_gating-around-pps-sequence.patch
+drm-i915-move-rawclk-from-runtime-to-display-runtime-info.patch
+drm-xe-display-drop-unused-rawclk_freq-and-runtime_info.patch
+drm-i915-psr-prevent-panel-replay-if-crc-calculation-is-enabled.patch
+drm-i915-display-don-t-enable-decompression-on-xe2-with-tile4.patch
+drm-xe-support-nomodeset-kernel-command-line-option.patch
+drm-xe-xe2hpg-add-wa_15016589081.patch
+drm-xe-move-enable-host-l2-vram-post-mcr-init.patch
+drm-xe-xe2hpg-introduce-performance-tuning-changes-for-xe2_hpg.patch
+drm-xe-xe2-introduce-performance-changes.patch
+drm-xe-xe2-add-performance-turning-changes.patch
+drm-xe-define-stateless_compression_ctrl-as-mcr-register.patch
+drm-xe-write-all-slices-if-its-mcr-register.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
