mips: ralink: update CPU clock index

Update CPU clock index to match the clock driver changes.

Fixes: d34db686a3d7 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
index 9db73fcac522ebc76240c2f17fc6fb676dc78821..5c1eb46ef5d07e11ba7791959e68261a78d71f9e 100644 (file)
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -21,16 +21,16 @@ static const char *clk_cpu(int *idx)
 {
        switch (ralink_soc) {
        case RT2880_SOC:
-               *idx = 0;
+               *idx = 1;
                return "ralink,rt2880-sysc";
        case RT3883_SOC:
-               *idx = 0;
+               *idx = 1;
                return "ralink,rt3883-sysc";
        case RT305X_SOC_RT3050:
-               *idx = 0;
+               *idx = 1;
                return "ralink,rt3050-sysc";
        case RT305X_SOC_RT3052:
-               *idx = 0;
+               *idx = 1;
                return "ralink,rt3052-sysc";
        case RT305X_SOC_RT3350:
                *idx = 1;