--- /dev/null
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq6lplus-olb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ6Lplus SoC system controller
+
+maintainers:
+ - Benoît Monin <benoit.monin@bootlin.com>
+ - Grégory Clement <gregory.clement@bootlin.com>
+ - Théo Lebrun <theo.lebrun@bootlin.com>
+ - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+
+description:
+ OLB ("Other Logic Block") is a hardware block grouping smaller blocks.
+ Clocks, resets, pinctrl are being handled from here. EyeQ6Lplus hosts
+ a single instance providing 22 clocks, two reset domains and one bank
+ of 32 pins.
+
+properties:
+ compatible:
+ items:
+ - const: mobileye,eyeq6lplus-olb
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ description:
+ First cell is reset domain index.
+ Second cell is reset index inside that domain.
+ const: 2
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ Input parent clock to all PLLs. Expected to be the main crystal.
+
+ clock-names:
+ const: ref
+
+patternProperties:
+ '-pins?$':
+ type: object
+ description: Pin muxing configuration.
+ $ref: /schemas/pinctrl/pinmux-node.yaml#
+ additionalProperties: false
+ properties:
+ pins: true
+ function:
+ enum: [gpio, timer0, timer1, uart_ssi, spi0, uart0, timer2, timer3,
+ timer_ext0, spi1, timer_ext1, ext_ref_clk, mipi_ref_clk]
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength: true
+ required:
+ - pins
+ - function
+ allOf:
+ - if:
+ properties:
+ function:
+ const: gpio
+ then:
+ properties:
+ pins:
+ items: # PA0 - PA31
+ pattern: '^(PA[1,2]?[0-9]|PA3[0,1])$'
+ - if:
+ properties:
+ function:
+ const: timer0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA0, PA1]
+ - if:
+ properties:
+ function:
+ const: timer1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA2, PA3]
+ - if:
+ properties:
+ function:
+ const: uart_ssi
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA4, PA5]
+ - if:
+ properties:
+ function:
+ const: spi0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA6, PA7, PA8, PA9, PA10]
+ - if:
+ properties:
+ function:
+ const: uart0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA11, PA12]
+ - if:
+ properties:
+ function:
+ const: timer2
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA13, PA14]
+ - if:
+ properties:
+ function:
+ const: timer3
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA15, PA16]
+ - if:
+ properties:
+ function:
+ const: timer_ext0
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA17, PA18, PA19, PA20]
+ - if:
+ properties:
+ function:
+ const: spi1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA21, PA22, PA23, PA24, PA25]
+ - if:
+ properties:
+ function:
+ const: timer_ext1
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA26, PA27, PA28, PA29]
+ - if:
+ properties:
+ function:
+ const: ext_ref_clk
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA30]
+ - if:
+ properties:
+ function:
+ const: mipi_ref_clk
+ then:
+ properties:
+ pins:
+ items:
+ enum: [PA31]
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ system-controller@e8400000 {
+ compatible = "mobileye,eyeq6lplus-olb", "syscon";
+ reg = <0 0xe8400000 0x0 0x80000>;
+ #reset-cells = <2>;
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "ref";
+ };
+ };
--- /dev/null
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Mobileye Vision Technologies Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H
+#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H
+
+#define EQ6LPC_PLL_CPU 0
+#define EQ6LPC_PLL_DDR 1
+#define EQ6LPC_PLL_PER 2
+#define EQ6LPC_PLL_VDI 3
+#define EQ6LPC_PLL_ACC 4
+
+#define EQ6LPC_CPU_OCC 5
+
+#define EQ6LPC_ACC_VDI 6
+#define EQ6LPC_ACC_OCC 7
+#define EQ6LPC_ACC_FCMU 8
+
+#define EQ6LPC_DDR_OCC 9
+
+#define EQ6LPC_PER_OCC 10
+#define EQ6LPC_PER_I2C_SER 11
+#define EQ6LPC_PER_PCLK 12
+#define EQ6LPC_PER_TSU 13
+#define EQ6LPC_PER_OSPI 14
+#define EQ6LPC_PER_GPIO 15
+#define EQ6LPC_PER_TIMER 16
+#define EQ6LPC_PER_I2C 17
+#define EQ6LPC_PER_UART 18
+#define EQ6LPC_PER_SPI 19
+#define EQ6LPC_PER_PERIPH 20
+
+#define EQ6LPC_VDI_OCC 21
+
+#endif