]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
EDAC/altera: Set DDR and SDMMC interrupt mask before registration
authorNiravkumar L Rabara <niravkumar.l.rabara@altera.com>
Fri, 25 Apr 2025 14:26:40 +0000 (07:26 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 4 Jun 2025 12:36:51 +0000 (14:36 +0200)
commit 6dbe3c5418c4368e824bff6ae4889257dd544892 upstream.

Mask DDR and SDMMC in probe function to avoid spurious interrupts before
registration.  Removed invalid register write to system manager.

Fixes: 1166fde93d5b ("EDAC, altera: Add Arria10 ECC memory init functions")
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: stable@kernel.org
Link: https://lore.kernel.org/20250425142640.33125-3-matthew.gerlach@altera.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/edac/altera_edac.c
drivers/edac/altera_edac.h

index bd36199d8fce7aa20ca8e217c7fc585d95daf49b..99aaada3a2d966dffb870700a728bae3d66ae501 100644 (file)
@@ -1006,9 +1006,6 @@ altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
                }
        }
 
-       /* Interrupt mode set to every SBERR */
-       regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
-                    ALTR_A10_ECC_INTMODE);
        /* Enable ECC */
        ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
                                        ALTR_A10_ECC_CTRL_OFST));
@@ -2089,6 +2086,10 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
                return PTR_ERR(edac->ecc_mgr_map);
        }
 
+       /* Set irq mask for DDR SBE to avoid any pending irq before registration */
+       regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
+                    (A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));
+
        edac->irq_chip.name = pdev->dev.of_node->name;
        edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
        edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
index 3727e72c8c2e70a98df2854608e1858bafb7d1fe..7248d24c4908d75e711933c4d954d82ac42d0aec 100644 (file)
@@ -249,6 +249,8 @@ struct altr_sdram_mc_data {
 #define A10_SYSMGR_ECC_INTMASK_SET_OFST   0x94
 #define A10_SYSMGR_ECC_INTMASK_CLR_OFST   0x98
 #define A10_SYSMGR_ECC_INTMASK_OCRAM      BIT(1)
+#define A10_SYSMGR_ECC_INTMASK_SDMMCB     BIT(16)
+#define A10_SYSMGR_ECC_INTMASK_DDR0       BIT(17)
 
 #define A10_SYSMGR_ECC_INTSTAT_SERR_OFST  0x9C
 #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST  0xA0