drm/i915/display: Remove FBC modulo 4 restriction for ADL-P+

WA:22010751166 does not apply past display version 12.  Or, in
other words, the FBC restriction where FBC is disabled for
non-modulo 4 plane sizes (including plane size + yoffset) is fixed
from display version 13 and onwards. Relax the restriction for the same.

v4: Dropped redundant commit message

v3: Update comments for clarity (Jonathan Cavitt)

v2: Update the macro for display version check (Vinod)

Suggested-by: Vidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Link: https://lore.kernel.org/r/20250904095338.300813-2-uma.shankar@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d4c5deff9cbe882893142aec1b35503ed1915254..9e097ed80bd1af41f47dfcae9aefc8b760651c04 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1550,14 +1550,14 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
         * having a Y offset that isn't divisible by 4 causes FIFO underrun
         * and screen flicker.
         */
-       if (DISPLAY_VER(display) >= 9 &&
+       if (IS_DISPLAY_VER(display, 9, 12) &&
            plane_state->view.color_plane[0].y & 3) {
                plane_state->no_fbc_reason = "plane start Y offset misaligned";
                return 0;
        }
 
        /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
-       if (DISPLAY_VER(display) >= 11 &&
+       if (IS_DISPLAY_VER(display, 9, 12) &&
            (plane_state->view.color_plane[0].y +
             (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
                plane_state->no_fbc_reason = "plane end Y offset misaligned";