4.14-stable patches

added patches:
	x86-cpu-fix-amd-erratum-1485-on-zen4-based-cpus.patch

diff --git a/queue-4.14/series b/queue-4.14/series
index 63b2198eca3107fa1a44c99d05038ec30ced5243..7f9ce55ee04a270d52a411e80595627038322cda 100644 (file)
--- a/queue-4.14/series
+++ b/queue-4.14/series
@@ -21,3 +21,4 @@ cgroup-remove-duplicates-in-cgroup-v1-tasks-file.patch
 pinctrl-avoid-unsafe-code-pattern-in-find_pinctrl.patch
 usb-gadget-udc-xilinx-replace-memcpy-with-memcpy_toio.patch
 usb-gadget-ncm-handle-decoding-of-multiple-ntb-s-in-unwrap-call.patch
+x86-cpu-fix-amd-erratum-1485-on-zen4-based-cpus.patch

diff --git a/queue-4.14/x86-cpu-fix-amd-erratum-1485-on-zen4-based-cpus.patch b/queue-4.14/x86-cpu-fix-amd-erratum-1485-on-zen4-based-cpus.patch
new file mode 100644 (file)
index 0000000..1ce492b
--- /dev/null
+++ b/queue-4.14/x86-cpu-fix-amd-erratum-1485-on-zen4-based-cpus.patch
@@ -0,0 +1,71 @@
+From f454b18e07f518bcd0c05af17a2239138bff52de Mon Sep 17 00:00:00 2001
+From: "Borislav Petkov (AMD)" <bp@alien8.de>
+Date: Sat, 7 Oct 2023 12:57:02 +0200
+Subject: x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Borislav Petkov (AMD) <bp@alien8.de>
+
+commit f454b18e07f518bcd0c05af17a2239138bff52de upstream.
+
+Fix erratum #1485 on Zen4 parts where running with STIBP disabled can
+cause an #UD exception. The performance impact of the fix is negligible.
+
+Reported-by: René Rebe <rene@exactcode.de>
+Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
+Tested-by: René Rebe <rene@exactcode.de>
+Cc: <stable@kernel.org>
+Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactcode.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/include/asm/msr-index.h |    4 ++++
+ arch/x86/kernel/cpu/amd.c        |    9 +++++++++
+ 2 files changed, 13 insertions(+)
+
+--- a/arch/x86/include/asm/msr-index.h
++++ b/arch/x86/include/asm/msr-index.h
+@@ -442,6 +442,10 @@
+ 
+ #define MSR_AMD64_VIRT_SPEC_CTRL      0xc001011f
+ 
++/* Zen4 */
++#define MSR_ZEN4_BP_CFG                       0xc001102e
++#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
++
+ /* Fam 17h MSRs */
+ #define MSR_F17H_IRPERF                       0xc00000e9
+ 
+--- a/arch/x86/kernel/cpu/amd.c
++++ b/arch/x86/kernel/cpu/amd.c
+@@ -24,6 +24,7 @@
+ 
+ static const int amd_erratum_383[];
+ static const int amd_erratum_400[];
++static const int amd_erratum_1485[];
+ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
+ 
+ /*
+@@ -974,6 +975,10 @@ static void init_amd(struct cpuinfo_x86
+       /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
+       if (!cpu_has(c, X86_FEATURE_XENPV))
+               set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
++
++      if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
++          cpu_has_amd_erratum(c, amd_erratum_1485))
++              msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
+ }
+ 
+ #ifdef CONFIG_X86_32
+@@ -1102,6 +1107,10 @@ static const int amd_erratum_383[] =
+       AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
+ 
+ 
++static const int amd_erratum_1485[] =
++      AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
++                         AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
++
+ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
+ {
+       int osvw_id = *erratum++;