spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

[ Upstream commit 9cf71eb0faef4bff01df4264841b8465382d7927 ]

While transmitting with rx_len == 0, the RX FIFO is not going to be
emptied in the interrupt handler. A subsequent transfer could then
read crap from the previous transfer out of the RX FIFO into the
start RX buffer. The core provides a register that will empty the RX and
TX FIFOs, so do that before each transfer.

Fixes: 9ac8d17694b6 ("spi: add support for microchip fpga spi controllers")
Signed-off-by: Steve Wilkins <steve.wilkins@raymarine.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20240715-flammable-provoke-459226d08e70@wendy
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/spi/spi-microchip-core.c b/drivers/spi/spi-microchip-core.c
index 78a073664f60b9d059be4e02d76f0c262434ac44..99c25e6a937fd034df4c38cf6dcec37fe1287a4c 100644 (file)
--- a/drivers/spi/spi-microchip-core.c
+++ b/drivers/spi/spi-microchip-core.c
@@ -91,6 +91,8 @@
 #define REG_CONTROL2           (0x28)
 #define REG_COMMAND            (0x2c)
 #define  COMMAND_CLRFRAMECNT   BIT(4)
+#define  COMMAND_TXFIFORST             BIT(3)
+#define  COMMAND_RXFIFORST             BIT(2)
 #define REG_PKTSIZE            (0x30)
 #define REG_CMD_SIZE           (0x34)
 #define REG_HWSTATUS           (0x38)
@@ -493,6 +495,8 @@ static int mchp_corespi_transfer_one(struct spi_controller *host,
        mchp_corespi_set_xfer_size(spi, (spi->tx_len > FIFO_DEPTH)
                                   ? FIFO_DEPTH : spi->tx_len);
 
+       mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST);
+
        mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);
 
        while (spi->tx_len)