Xilinx: ARM: spi: Removed usage of bit 1 on interrupt status register

Bit 1 on qspi.Intr_status_REG is reserved and it shouldn't be
used in driver, so removed it's usage from qspi driver.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 94353976e6f0bb04ca9189101aca68c1390d9ac7..3a002fd9785cb03f882a3227c4cb86bd626997b7 100755 (executable)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -143,13 +143,11 @@ typedef enum irqreturn irqreturn_t;
  * All the four interrupt registers (Status/Mask/Enable/Disable) have the same
  * bit definitions.
  */
-#define XQSPIPSS_IXR_MODF_MASK         0x00000002 /* QSPI Mode Fault */
 #define XQSPIPSS_IXR_TXNFULL_MASK      0x00000004 /* QSPI TX FIFO Overflow */
 #define XQSPIPSS_IXR_TXFULL_MASK       0x00000008 /* QSPI TX FIFO is full */
 #define XQSPIPSS_IXR_RXNEMTY_MASK      0x00000010 /* QSPI RX FIFO Not Empty */
 #define XQSPIPSS_IXR_ALL_MASK          (XQSPIPSS_IXR_TXNFULL_MASK | \
-                                        XQSPIPSS_IXR_RXNEMTY_MASK | \
-                                        XQSPIPSS_IXR_MODF_MASK)
+                                        XQSPIPSS_IXR_RXNEMTY_MASK)
 
 /*
  * QSPI Enable Register bit Masks
@@ -679,20 +677,7 @@ static int xqspips_irq_poll(struct xqspips *xqspi)
        xqspips_write(xqspi->regs + XQSPIPSS_IDIS_OFFSET,
                        XQSPIPSS_IXR_ALL_MASK);
 #endif
-
-       if (intr_status & XQSPIPSS_IXR_MODF_MASK) {
-               /* Indicate that transfer is completed, the SPI subsystem will
-                * identify the error as the remaining bytes to be
-                * transferred is non-zero */
-#ifdef LINUX_ONLY_NOT_UBOOT
-               complete(&xqspi->done);
-#else
-               /* u-boot: return "operation complete" */
-               xqspips_write(xqspi->regs + XQSPIPSS_IDIS_OFFSET,
-                       XQSPIPSS_IXR_ALL_MASK);
-               return 1;
-#endif
-       } else if ((intr_status & XQSPIPSS_IXR_TXNFULL_MASK) ||
+       if ((intr_status & XQSPIPSS_IXR_TXNFULL_MASK) ||
                   (intr_status & XQSPIPSS_IXR_RXNEMTY_MASK)) {
                /* This bit is set when Tx FIFO has < THRESHOLD entries. We have
                   the THRESHOLD value set to 1, so this bit indicates Tx FIFO