]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
ARM64: zynqmp: Enable CLK and SPL_CLK by default
authorMichal Simek <michal.simek@xilinx.com>
Thu, 14 Jul 2016 12:41:28 +0000 (14:41 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 15 Jul 2016 07:05:04 +0000 (09:05 +0200)
Serial driver starts to use clk framework that's why
enable it by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/Kconfig
configs/xilinx_zynqmp_ep_defconfig
configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig
configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
configs/xilinx_zynqmp_zcu102_defconfig
configs/xilinx_zynqmp_zcu102_revB_defconfig

index 3237a74f722358bdb76207fa0244eeb1fb3a403f..f01eadf69f5ec3a9168f34d4427039a7a07fcca5 100644 (file)
@@ -669,6 +669,8 @@ config ARCH_ZYNQMP
        select OF_CONTROL
        select DM_SERIAL
        select SUPPORT_SPL
+       select CLK
+       select SPL_CLK
 
 config TEGRA
        bool "NVIDIA Tegra"
index 91790b5bf6139566ce53f5bd8cea89dbb7ef3863..b0f7ae44743d8c8d6ea7404f8057a686d195da52 100644 (file)
@@ -50,8 +50,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
index 3054b2d38f5dfa278449c85407c0e9f0eb940aae..3f23a8ff6c6d8dce44dd05f64d783fc6272af72f 100644 (file)
@@ -41,8 +41,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
index ceff07d4449b95f59169b10c82006ba8e2bd1b1b..9fa156227ba2f20450b7d5320bb3746d422aaa96 100644 (file)
@@ -38,8 +38,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_NAND_ARASAN=y
index 33e4b2d869d199b8f79bae60bb23c6a08b1c2e9e..cb0d135a403098168a981bb30d64cffef46dc367 100644 (file)
@@ -39,8 +39,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
index 00368ca128ee3e4006c32238b86360c00bd218d4..efa7b8c40c53614844167d12ef32ca17873d607e 100644 (file)
@@ -34,8 +34,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
index b4aa8c1066698c48c8d1b953342eb1b306e3b168..a6818c16c4350256a264e1ad9fcfa735e9ed6d33 100644 (file)
@@ -33,8 +33,6 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
index cbbc5a3a75dfb85cbc48719474a7ab2e505e003a..2feb8983bb2cedf7fcb21ecaa6e7630b8a64e82c 100644 (file)
@@ -40,8 +40,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
index 5d5545765a1534b8029c86f1f04f0dd149d08220..686fb03b38baf01e795d9cbdcc6ad2c64e1cc856 100644 (file)
@@ -40,8 +40,6 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y