clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks

[ Upstream commit 99a8f8764b70158a712992640a6be46a8fd79d15 ]

GPLL clock rates are fixed and shouldn't be scaled based on the request
from dependent clocks. Doing so will result in the unexpected behaviour.
So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.

----
Changes in V2:
	- No changes

Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-4-c8ceb1a37680@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 8f430367299e667bab2dcea1b9c7142cc7d2f2cc..e8190108e1aef394eb546981b1cea8a6f6f0e2ba 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -87,7 +87,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
                        &gpll0_main.clkr.hw
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_fixed_factor_ops,
        },
 };
@@ -102,7 +101,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
                        &gpll0_main.clkr.hw
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
        },
 };
@@ -132,7 +130,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
                        &gpll4_main.clkr.hw
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
        },
 };
@@ -162,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
                        &gpll2_main.clkr.hw
                },
                .num_parents = 1,
-               .flags = CLK_SET_RATE_PARENT,
                .ops = &clk_alpha_pll_postdiv_ro_ops,
        },
 };