wifi: rtl8xxxu: 8188f: Limit TX power index

[ Upstream commit d0b4b8ef083ca46d5d318e66a30fb80e0abbb90d ]

TX power index is read from the efuse on init, the values get written to
the TX power registers when the channel gets switched.

When the chip has not yet been calibrated, the efuse values are 0xFF,
which on some boards leads to USB timeouts for reading/writing registers
after the first frames have been sent.

The vendor driver (v5.11.5-1) checks for these invalid values and sets
default values instead. Implement something similar in
rtl8188fu_parse_efuse().

Fixes: c888183b21f3 ("wifi: rtl8xxxu: Support new chip RTL8188FU")
Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de>
Reviewed-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20240624140037.231657-1-martin.kaistra@linutronix.de
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/wireless/realtek/rtl8xxxu/8188f.c b/drivers/net/wireless/realtek/rtl8xxxu/8188f.c
index bd5a0603b4a235b0ffdd1f25faee78ba37bf6c8c..3abf14d7044f37b69bf0b7337cfc944d43f65d47 100644 (file)
--- a/drivers/net/wireless/realtek/rtl8xxxu/8188f.c
+++ b/drivers/net/wireless/realtek/rtl8xxxu/8188f.c
@@ -697,9 +697,14 @@ static void rtl8188fu_init_statistics(struct rtl8xxxu_priv *priv)
        rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
 }
 
+#define TX_POWER_INDEX_MAX 0x3F
+#define TX_POWER_INDEX_DEFAULT_CCK 0x22
+#define TX_POWER_INDEX_DEFAULT_HT40 0x27
+
 static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv)
 {
        struct rtl8188fu_efuse *efuse = &priv->efuse_wifi.efuse8188fu;
+       int i;
 
        if (efuse->rtl_id != cpu_to_le16(0x8129))
                return -EINVAL;
@@ -713,6 +718,16 @@ static int rtl8188fu_parse_efuse(struct rtl8xxxu_priv *priv)
               efuse->tx_power_index_A.ht40_base,
               sizeof(efuse->tx_power_index_A.ht40_base));
 
+       for (i = 0; i < ARRAY_SIZE(priv->cck_tx_power_index_A); i++) {
+               if (priv->cck_tx_power_index_A[i] > TX_POWER_INDEX_MAX)
+                       priv->cck_tx_power_index_A[i] = TX_POWER_INDEX_DEFAULT_CCK;
+       }
+
+       for (i = 0; i < ARRAY_SIZE(priv->ht40_1s_tx_power_index_A); i++) {
+               if (priv->ht40_1s_tx_power_index_A[i] > TX_POWER_INDEX_MAX)
+                       priv->ht40_1s_tx_power_index_A[i] = TX_POWER_INDEX_DEFAULT_HT40;
+       }
+
        priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
        priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;