drm/amd/display: Add gpuvm and hvm params to dml21

[Why & How]
Add missing params to display configuration for dml21

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
index bf5e7f4e04167fad6b3f1874518dbad820aa8702..75a27999796156e7e64e36b0ccab3e9ef86582df 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
@@ -734,8 +734,12 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_s
        memset(&dml_ctx->v21.dml_to_dc_pipe_mapping, 0, sizeof(struct dml2_dml_to_dc_pipe_mapping));
 
        dml_dispcfg->gpuvm_enable = dml_ctx->config.gpuvm_enable;
-       dml_dispcfg->gpuvm_max_page_table_levels = 4;
-       dml_dispcfg->hostvm_enable = false;
+       if (dml_ctx->v21.dml_init.soc_bb.gpuvm_max_page_table_levels)
+               dml_dispcfg->gpuvm_max_page_table_levels = dml_ctx->v21.dml_init.soc_bb.gpuvm_max_page_table_levels;
+       else
+               dml_dispcfg->gpuvm_max_page_table_levels = 4;
+       dml_dispcfg->hostvm_enable = dml_ctx->config.hostvm_enable;
+       dml_dispcfg->hostvm_max_non_cached_page_table_levels = dml_ctx->v21.dml_init.soc_bb.hostvm_max_non_cached_page_table_levels;
        dml_dispcfg->minimize_det_reallocation = true;
        dml_dispcfg->overrides.enable_subvp_implicit_pmo = true;
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h
index c4cce870877a144329dbfbda0a1fa463d8d838a2..ddbb8dfa9ff885c31be1c608b8445bf0bf73cc34 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_soc_parameter_types.h
@@ -160,6 +160,8 @@ struct dml2_soc_bb {
        unsigned long return_bus_width_bytes;
        unsigned long hostvm_min_page_size_kbytes;
        unsigned long gpuvm_min_page_size_kbytes;
+       unsigned int hostvm_max_non_cached_page_table_levels;
+       unsigned int gpuvm_max_page_table_levels;
        double phy_downspread_percent;
        double dcn_downspread_percent;
        double dispclk_dppclk_vco_speed_mhz;

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h
index 9a9c27962f681b763469a778303981903b7a478a..5ee489682f2ead38f79c67d255da264721d66a9e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_wrapper.h
@@ -239,6 +239,7 @@ struct dml2_configuration_options {
 
        bool use_clock_dc_limits;
        bool gpuvm_enable;
+       bool hostvm_enable;
        bool force_tdlut_enable;
        void *bb_from_dmub;
 };