arm64: dt: add nanopi r2c (plus)

Signed-off-by: Arne Fitzenreiter <arne_f@ipfire.org>

diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 1ee13911f1d15ee28ffb89104ea90ca1b5f58365..a87b71b9be340e66d6f4ca35a8fdf82c8991356e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -10,6 +10,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-oc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s-oc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-oc.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-oc.dts
new file mode 100644 (file)
index 0000000..617bcef
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-oc.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * overclock Nanopi R2C to 1.5 Ghz
+ */
+
+/dts-v1/;
+
+#include "rk3328-nanopi-r2c.dts"
+
+/ {
+       model = "FriendlyElec NanoPi R2C OC";
+
+       cpu0_opp_table: opp-table-0 {
+               opp-1392000000 {
+                       opp-hz = /bits/ 64 <1392000000>;
+                       opp-microvolt = <1350000>;
+                       clock-latency-ns = <40000>;
+               };
+               opp-1512000000 {
+                       opp-hz = /bits/ 64 <1512000000>;
+                       opp-microvolt = <1400000>;
+                       clock-latency-ns = <40000>;
+               };
+       };
+};

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
new file mode 100644 (file)
index 0000000..6d36562
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3328-nanopi-r2s.dts"
+
+/ {
+       model = "FriendlyElec NanoPi R2C";
+       compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
+
+       aliases {
+               mmc0 = &sdmmc;
+               mmc1 = &emmc;
+       };
+};
+
+&emmc {
+       bus-width = <8>;
+       cap-mmc-highspeed;
+       max-frequency = <150000000>;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       non-removable;
+       pinctrl-names = "default";
+       pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+       vmmc-supply = <&vcc_io_33>;
+       vqmmc-supply = <&vcc18_emmc>;
+       status = "okay";
+};
+
+&gmac2io {
+       phy-handle = <&yt8521s>;
+       tx_delay = <0x22>;
+       rx_delay = <0x12>;
+
+       mdio {
+               /delete-node/ ethernet-phy@1;
+
+               yt8521s: ethernet-phy@3 {
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       reg = <3>;
+
+                       motorcomm,clk-out-frequency-hz = <125000000>;
+                       motorcomm,keep-pll-enabled;
+                       motorcomm,auto-sleep-disabled;
+
+                       pinctrl-0 = <&eth_phy_reset_pin>;
+                       pinctrl-names = "default";
+                       reset-assert-us = <10000>;
+                       reset-deassert-us = <50000>;
+                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+               };
+       };
+};