--- /dev/null
+From 3c4aa91f21f65b7b40bdfb015eacbcb8453ccae2 Mon Sep 17 00:00:00 2001
+From: Mark Nelson <mdnelson8@gmail.com>
+Date: Mon, 27 Jun 2011 16:33:44 +1000
+Subject: ahci: Enable SB600 64bit DMA on Asus M3A
+
+From: Mark Nelson <mdnelson8@gmail.com>
+
+commit 3c4aa91f21f65b7b40bdfb015eacbcb8453ccae2 upstream.
+
+Like e65cc194f7628ecaa02462f22f42fb09b50dcd49 this patch enables 64bit DMA
+for the AHCI SATA controller of a board that has the SB600 southbridge. In
+this case though we're enabling 64bit DMA for the Asus M3A motherboard. It
+is a new enough board that all of the BIOS releases since the initial
+release (0301 from 2007-10-22) work correctly with 64bit DMA enabled.
+
+Signed-off-by: Mark Nelson <mdnelson8@gmail.com>
+Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ drivers/ata/ahci.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/ata/ahci.c
++++ b/drivers/ata/ahci.c
+@@ -812,6 +812,18 @@ static bool ahci_sb600_enable_64bit(stru
+ DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
+ },
+ },
++ /*
++ * All BIOS versions for the Asus M3A support 64bit DMA.
++ * (all release versions from 0301 to 1206 were tested)
++ */
++ {
++ .ident = "ASUS M3A",
++ .matches = {
++ DMI_MATCH(DMI_BOARD_VENDOR,
++ "ASUSTeK Computer INC."),
++ DMI_MATCH(DMI_BOARD_NAME, "M3A"),
++ },
++ },
+ { }
+ };
+ const struct dmi_system_id *match;
--- /dev/null
+From bd7100099a46b59f433dd15ad60adbb4d4f3d625 Mon Sep 17 00:00:00 2001
+From: "Rafael J. Wysocki" <rjw@sisk.pl>
+Date: Thu, 2 Jun 2011 21:06:48 +0200
+Subject: MIPS: PM: Use struct syscore_ops instead of sysdevs for PM
+ (v2)
+
+From: "Rafael J. Wysocki" <rjw@sisk.pl>
+
+commit bd7100099a46b59f433dd15ad60adbb4d4f3d625 upstream.
+
+Convert some MIPS architecture's code to using struct syscore_ops
+objects for power management instead of sysdev classes and sysdevs.
+
+This simplifies the code and reduces the kernel's memory footprint.
+It also is necessary for removing sysdevs from the kernel entirely in
+the future.
+
+Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
+Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
+Acked-and-tested-by: Lars-Peter Clausen <lars@metafoo.de>
+Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
+Cc: linux-kernel@vger.kernel.org
+Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
+Patchwork: http://patchwork.linux-mips.org/patch/2431/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
+
+---
+ arch/mips/jz4740/gpio.c | 52 ++++++++++++++++++++----------------------------
+ 1 file changed, 22 insertions(+), 30 deletions(-)
+
+--- a/arch/mips/jz4740/gpio.c
++++ b/arch/mips/jz4740/gpio.c
+@@ -18,7 +18,7 @@
+ #include <linux/init.h>
+
+ #include <linux/spinlock.h>
+-#include <linux/sysdev.h>
++#include <linux/syscore_ops.h>
+ #include <linux/io.h>
+ #include <linux/gpio.h>
+ #include <linux/delay.h>
+@@ -86,7 +86,6 @@ struct jz_gpio_chip {
+ spinlock_t lock;
+
+ struct gpio_chip gpio_chip;
+- struct sys_device sysdev;
+ };
+
+ static struct jz_gpio_chip jz4740_gpio_chips[];
+@@ -459,49 +458,47 @@ static struct jz_gpio_chip jz4740_gpio_c
+ JZ4740_GPIO_CHIP(D),
+ };
+
+-static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
++static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip)
+ {
+- return container_of(dev, struct jz_gpio_chip, sysdev);
++ chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
++ writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
++ writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
+ }
+
+-static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
++static int jz4740_gpio_suspend(void)
+ {
+- struct jz_gpio_chip *chip = sysdev_to_chip(dev);
++ int i;
+
+- chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
+- writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
+- writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
++ for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++)
++ jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]);
+
+ return 0;
+ }
+
+-static int jz4740_gpio_resume(struct sys_device *dev)
++static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip)
+ {
+- struct jz_gpio_chip *chip = sysdev_to_chip(dev);
+ uint32_t mask = chip->suspend_mask;
+
+ writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
+ writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
++}
+
+- return 0;
++static void jz4740_gpio_resume(void)
++{
++ int i;
++
++ for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--)
++ jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]);
+ }
+
+-static struct sysdev_class jz4740_gpio_sysdev_class = {
+- .name = "gpio",
++static struct syscore_ops jz4740_gpio_syscore_ops = {
+ .suspend = jz4740_gpio_suspend,
+ .resume = jz4740_gpio_resume,
+ };
+
+-static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
++static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
+ {
+- int ret, irq;
+-
+- chip->sysdev.id = id;
+- chip->sysdev.cls = &jz4740_gpio_sysdev_class;
+- ret = sysdev_register(&chip->sysdev);
+-
+- if (ret)
+- return ret;
++ int irq;
+
+ spin_lock_init(&chip->lock);
+
+@@ -519,22 +516,17 @@ static int jz4740_gpio_chip_init(struct
+ irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
+ handle_level_irq);
+ }
+-
+- return 0;
+ }
+
+ static int __init jz4740_gpio_init(void)
+ {
+ unsigned int i;
+- int ret;
+-
+- ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
+- if (ret)
+- return ret;
+
+ for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
+ jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
+
++ register_syscore_ops(&jz4740_gpio_syscore_ops);
++
+ printk(KERN_INFO "JZ4740 GPIO initialized\n");
+
+ return 0;
projects / thirdparty / kernel / stable-queue.git / commitdiff
