]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
spi-rockchip: Fix register out of bounds access
authorLuis de Arquer <luis.dearquer@inertim.com>
Fri, 21 Mar 2025 12:57:53 +0000 (13:57 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 4 Jun 2025 12:41:55 +0000 (14:41 +0200)
[ Upstream commit 7a874e8b54ea21094f7fd2d428b164394c6cb316 ]

Do not write native chip select stuff for GPIO chip selects.
GPIOs can be numbered much higher than native CS.
Also, it makes no sense.

Signed-off-by: Luis de Arquer <luis.dearquer@inertim.com>
Link: https://patch.msgid.link/365ccddfba110549202b3520f4401a6a936e82a8.camel@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/spi/spi-rockchip.c

index 1f374cf4d6f65c8ff01d6c0c55bef93bedf458ed..1615f935c8f03f9c08198ca1ef6903f4b8757d66 100644 (file)
@@ -542,7 +542,7 @@ static int rockchip_spi_config(struct rockchip_spi *rs,
        cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
        if (spi->mode & SPI_LSB_FIRST)
                cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
-       if (spi->mode & SPI_CS_HIGH)
+       if ((spi->mode & SPI_CS_HIGH) && !(spi_get_csgpiod(spi, 0)))
                cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET;
 
        if (xfer->rx_buf && xfer->tx_buf)