drm/msm/a6xx: Add soft fuse detection support

Recent chipsets like Glymur supports a new mechanism for SKU detection.
A new CX_MISC register exposes the combined (or final) speedbin value
from both HW fuse register and the Soft Fuse register. Implement this new
SKU detection along with a new quirk to identify the GPUs that has soft
fuse support.

There is a side effect of this patch on A4x and older series. The
speedbin field in the MSM_PARAM_CHIPID will be 0 instead of 0xffff. This
should be okay as Mesa correctly handles it. Speedbin was not even a
thing when those GPUs' support were added.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714676/
Message-ID: <20260327-a8xx-gpu-batch2-v2-12-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 79a441e91fa1852ef36ae9b7de4f4659057661b2..d7ed3225f635ab0542043f9ce07852f1dce5ef0a 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1731,6 +1731,7 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
        struct adreno_gpu *adreno_gpu;
        struct msm_gpu *gpu;
        unsigned int nr_rings;
+       u32 speedbin;
        int ret;
 
        a5xx_gpu = kzalloc(sizeof(*a5xx_gpu), GFP_KERNEL);
@@ -1757,6 +1758,11 @@ static struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
                return ERR_PTR(ret);
        }
 
+       /* Set the speedbin value that is passed to userspace */
+       if (adreno_read_speedbin(&pdev->dev, &speedbin) || !speedbin)
+               speedbin = 0xffff;
+       adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
+
        msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
                                  a5xx_fault_handler);
 

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 252a040e02b065fdf86961a0b472d31072210ec1..fb52557e22d82a53d2e4d0970aa2111fc94383ca 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2546,13 +2546,33 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse)
        return UINT_MAX;
 }
 
-static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info)
+static int a6xx_read_speedbin(struct device *dev, struct a6xx_gpu *a6xx_gpu,
+               const struct adreno_info *info, u32 *speedbin)
+{
+       int ret;
+
+       /* Use speedbin fuse if present. Otherwise, fallback to softfuse */
+       ret = adreno_read_speedbin(dev, speedbin);
+       if (ret != -ENOENT)
+               return ret;
+
+       if (info->quirks & ADRENO_QUIRK_SOFTFUSE) {
+               *speedbin = a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS);
+               *speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin);
+               return 0;
+       }
+
+       return -ENOENT;
+}
+
+static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
+               const struct adreno_info *info)
 {
        u32 supp_hw;
        u32 speedbin;
        int ret;
 
-       ret = adreno_read_speedbin(dev, &speedbin);
+       ret = a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin);
        /*
         * -ENOENT means that the platform doesn't support speedbin which is
         * fine
@@ -2586,11 +2606,13 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
        struct msm_drm_private *priv = dev->dev_private;
        struct platform_device *pdev = priv->gpu_pdev;
        struct adreno_platform_config *config = pdev->dev.platform_data;
+       const struct adreno_info *info = config->info;
        struct device_node *node;
        struct a6xx_gpu *a6xx_gpu;
        struct adreno_gpu *adreno_gpu;
        struct msm_gpu *gpu;
        extern int enable_preemption;
+       u32 speedbin;
        bool is_a7xx;
        int ret, nr_rings = 1;
 
@@ -2614,14 +2636,14 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
        adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper");
 
        adreno_gpu->base.hw_apriv =
-               !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
+               !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV);
 
        /* gpu->info only gets assigned in adreno_gpu_init(). A8x is included intentionally */
-       is_a7xx = config->info->family >= ADRENO_7XX_GEN1;
+       is_a7xx = info->family >= ADRENO_7XX_GEN1;
 
        a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx);
 
-       ret = a6xx_set_supported_hw(&pdev->dev, config->info);
+       ret = a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info);
        if (ret) {
                a6xx_llc_slices_destroy(a6xx_gpu);
                kfree(a6xx_gpu);
@@ -2629,15 +2651,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
        }
 
        if ((enable_preemption == 1) || (enable_preemption == -1 &&
-           (config->info->quirks & ADRENO_QUIRK_PREEMPTION)))
+           (info->quirks & ADRENO_QUIRK_PREEMPTION)))
                nr_rings = 4;
 
-       ret = adreno_gpu_init(dev, pdev, adreno_gpu, config->info->funcs, nr_rings);
+       ret = adreno_gpu_init(dev, pdev, adreno_gpu, info->funcs, nr_rings);
        if (ret) {
                a6xx_destroy(&(a6xx_gpu->base.base));
                return ERR_PTR(ret);
        }
 
+       /* Set the speedbin value that is passed to userspace */
+       if (a6xx_read_speedbin(&pdev->dev, a6xx_gpu, info, &speedbin) || !speedbin)
+               speedbin = 0xffff;
+       adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
+
        /*
         * For now only clamp to idle freq for devices where this is known not
         * to cause power supply issues:

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 785e99fb5bd5d48566cfbd4dd1a85078e66991d2..0dbeb332f8d1d0b8887bd2a99422553d04e99586 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -1182,7 +1182,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
        struct msm_gpu_config adreno_gpu_config  = { 0 };
        struct msm_gpu *gpu = &adreno_gpu->base;
        const char *gpu_name;
-       u32 speedbin;
        int ret;
 
        adreno_gpu->funcs = funcs;
@@ -1211,10 +1210,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
                        devm_pm_opp_set_clkname(dev, "core");
        }
 
-       if (adreno_read_speedbin(dev, &speedbin) || !speedbin)
-               speedbin = 0xffff;
-       adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin);
-
        gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT,
                        ADRENO_CHIPID_ARGS(config->chip_id));
        if (!gpu_name)

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 41b0e376ee31a75f9240c079189af5a891dc96a9..834f6fd2a89eaefa4689541bc35963b8f08ea36f 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -63,6 +63,7 @@ enum adreno_family {
 #define ADRENO_QUIRK_PREEMPTION                        BIT(5)
 #define ADRENO_QUIRK_4GB_VA                    BIT(6)
 #define ADRENO_QUIRK_IFPC                      BIT(7)
+#define ADRENO_QUIRK_SOFTFUSE                  BIT(8)
 
 /* Helper for formating the chip_id in the way that userspace tools like
  * crashdec expect.

diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
index 3941e75107545d6d30cbf60f2560b780b6324535..2309870f503175670b4b7fdcd7de531e932460db 100644 (file)
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -5016,6 +5016,10 @@ by a particular renderpass/blit.
                <bitfield pos="1" name="LPAC" type="boolean"/>
                <bitfield pos="2" name="RAYTRACING" type="boolean"/>
        </reg32>
+       <reg32 offset="0x0405" name="CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS" variants="A8XX-">
+               <bitfield high="8" low="0" name="FINALFREQLIMIT"/>
+               <bitfield pos="24" name="SOFTSKUDISABLED" type="boolean"/>
+       </reg32>
 </domain>
 
 </database>