dt-bindings: clock: qcom: Add SM8750 GPU clocks

The SM8750 features a "traditional" GPU_CC block, much of which is
controlled through the GMU microcontroller. GPU_CC block requires the MX
and CX rail control and thus add the corresponding power-domains and
require-opps. Additionally, there's an separate GX_CC block, where
the GX GDSC is moved.

Update the bindings to accommodate for SM8750 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-1-78292b40b053@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
index 55bf3f8110171e9d14a2d0f7ba8e0089a31177cc..466c884aa2bab2d45fe51b283d6e4ccb2434e494 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml
@@ -22,6 +22,7 @@ properties:
     enum:
       - qcom,glymur-gxclkctl
       - qcom,kaanapali-gxclkctl
+      - qcom,sm8750-gxclkctl
 
   power-domains:
     description:

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
index 5993804c91fa564b29f8dd0650c9efad498f543d..fdbdf605ee695637512ce4f98c9b6fcfacb9154f 100644 (file)
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
@@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller on SM8450
 
 maintainers:
   - Konrad Dybcio <konradybcio@kernel.org>
+  - Taniya Das <taniya.das@oss.qualcomm.com>
 
 description: |
   Qualcomm graphics clock control module provides the clocks, resets and power
@@ -23,6 +24,7 @@ description: |
     include/dt-bindings/clock/qcom,sm8550-gpucc.h
     include/dt-bindings/reset/qcom,sm8450-gpucc.h
     include/dt-bindings/reset/qcom,sm8650-gpucc.h
+    include/dt-bindings/reset/qcom,sm8750-gpucc.h
     include/dt-bindings/reset/qcom,x1e80100-gpucc.h
 
 properties:
@@ -37,6 +39,7 @@ properties:
       - qcom,sm8475-gpucc
       - qcom,sm8550-gpucc
       - qcom,sm8650-gpucc
+      - qcom,sm8750-gpucc
       - qcom,x1e80100-gpucc
       - qcom,x1p42100-gpucc
 
@@ -46,6 +49,16 @@ properties:
       - description: GPLL0 main branch source
       - description: GPLL0 div branch source
 
+  power-domains:
+    items:
+      - description: A phandle to the MX power-domain
+      - description: A phandle to the CX power-domain
+
+  required-opps:
+    items:
+      - description: A phandle to an OPP node describing MX performance points
+      - description: A phandle to an OPP node describing CX performance points
+
 required:
   - compatible
   - clocks
@@ -53,6 +66,16 @@ required:
 
 allOf:
   - $ref: qcom,gcc.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8750-gpucc
+    then:
+      required:
+        - power-domains
+        - required-opps
 
 unevaluatedProperties: false
 

diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bindings/clock/qcom,sm8750-gpucc.h
new file mode 100644 (file)
index 0000000..e2143d9
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK                                         0
+#define GPU_CC_CB_CLK                                          1
+#define GPU_CC_CX_ACCU_SHIFT_CLK                               2
+#define GPU_CC_CX_FF_CLK                                       3
+#define GPU_CC_CX_GMU_CLK                                      4
+#define GPU_CC_CXO_AON_CLK                                     5
+#define GPU_CC_CXO_CLK                                         6
+#define GPU_CC_DEMET_CLK                                       7
+#define GPU_CC_DPM_CLK                                         8
+#define GPU_CC_FF_CLK_SRC                                      9
+#define GPU_CC_FREQ_MEASURE_CLK                                        10
+#define GPU_CC_GMU_CLK_SRC                                     11
+#define GPU_CC_GX_ACCU_SHIFT_CLK                               12
+#define GPU_CC_GX_ACD_AHB_FF_CLK                               13
+#define GPU_CC_GX_AHB_FF_CLK                                   14
+#define GPU_CC_GX_GMU_CLK                                      15
+#define GPU_CC_GX_RCG_AHB_FF_CLK                               16
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK                         17
+#define GPU_CC_HUB_AON_CLK                                     18
+#define GPU_CC_HUB_CLK_SRC                                     19
+#define GPU_CC_HUB_CX_INT_CLK                                  20
+#define GPU_CC_HUB_DIV_CLK_SRC                                 21
+#define GPU_CC_MEMNOC_GFX_CLK                                  22
+#define GPU_CC_PLL0                                            23
+#define GPU_CC_PLL0_OUT_EVEN                                   24
+#define GPU_CC_RSCC_HUB_AON_CLK                                        25
+#define GPU_CC_RSCC_XO_AON_CLK                                 26
+#define GPU_CC_SLEEP_CLK                                       27
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC                                         0
+
+/* GPU_CC resets */
+#define GPU_CC_GPU_CC_CB_BCR                                   0
+#define GPU_CC_GPU_CC_CX_BCR                                   1
+#define GPU_CC_GPU_CC_FAST_HUB_BCR                             2
+#define GPU_CC_GPU_CC_FF_BCR                                   3
+#define GPU_CC_GPU_CC_GMU_BCR                                  4
+#define GPU_CC_GPU_CC_GX_BCR                                   5
+#define GPU_CC_GPU_CC_XO_BCR                                   6
+
+#endif