]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/commitdiff
3.7-stable patches
authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 15 Jan 2013 13:37:55 +0000 (05:37 -0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 15 Jan 2013 13:37:55 +0000 (05:37 -0800)
added patches:
drm-i915-disable-cpt-phase-pointer-fdi-rx-workaround.patch

queue-3.7/drm-i915-disable-cpt-phase-pointer-fdi-rx-workaround.patch [new file with mode: 0644]
queue-3.7/series

diff --git a/queue-3.7/drm-i915-disable-cpt-phase-pointer-fdi-rx-workaround.patch b/queue-3.7/drm-i915-disable-cpt-phase-pointer-fdi-rx-workaround.patch
new file mode 100644 (file)
index 0000000..70836de
--- /dev/null
@@ -0,0 +1,123 @@
+From 539526b4137bc0e7a8806c38c8522f226814a0e6 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+Date: Sat, 8 Dec 2012 12:58:33 +0100
+Subject: drm/i915: disable cpt phase pointer fdi rx workaround
+
+From: Daniel Vetter <daniel.vetter@ffwll.ch>
+
+commit 539526b4137bc0e7a8806c38c8522f226814a0e6 upstream.
+
+We've originally added this in
+
+commit 291427f5fdadec6e4be2924172e83588880e1539
+Author: Jesse Barnes <jbarnes@virtuousgeek.org>
+Date:   Fri Jul 29 12:42:37 2011 -0700
+
+    drm/i915: apply phase pointer override on SNB+ too
+
+and then copy-pasted it over to ivb/ppt. The w/a was originally added
+for ilk/ibx in
+
+commit 5b2adf897146edeac6a1e438fb67b5a53dbbdf34
+Author: Jesse Barnes <jbarnes@virtuousgeek.org>
+Date:   Thu Oct 7 16:01:15 2010 -0700
+
+    drm/i915: add Ironlake clock gating workaround for FDI link training
+
+and fixed up a bit in
+
+commit 6f06ce184c765fd8d50669a8d12fdd566c920859
+Author: Jesse Barnes <jbarnes@virtuousgeek.org>
+Date:   Tue Jan 4 15:09:38 2011 -0800
+
+    drm/i915: set phase sync pointer override enable before setting phase sync pointer
+
+It turns out that this w/a isn't actually required on cpt/ppt and
+positively harmful on ivb/ppt when using fdi B/C links - it results in
+a black screen occasionally, with seemingfully everything working as
+it should. The only failure indication I've found in the hw is that
+eventually (but not right after the modeset completes) a pipe underrun
+is signalled.
+
+Big thanks to Arthur Runyan for all the ideas for registers to check
+and changes to test, otherwise I couldn't ever have tracked this down!
+
+Cc: "Runyan, Arthur J" <arthur.j.runyan@intel.com>
+Cc: stable@vger.kernel.org
+Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: CAI Qian <caiqian@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/intel_display.c |   31 -------------------------------
+ 1 file changed, 31 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -2302,18 +2302,6 @@ static void intel_fdi_normal_train(struc
+                          FDI_FE_ERRC_ENABLE);
+ }
+-static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+-{
+-      struct drm_i915_private *dev_priv = dev->dev_private;
+-      u32 flags = I915_READ(SOUTH_CHICKEN1);
+-
+-      flags |= FDI_PHASE_SYNC_OVR(pipe);
+-      I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+-      flags |= FDI_PHASE_SYNC_EN(pipe);
+-      I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+-      POSTING_READ(SOUTH_CHICKEN1);
+-}
+-
+ /* The FDI link training functions for ILK/Ibexpeak. */
+ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
+ {
+@@ -2464,9 +2452,6 @@ static void gen6_fdi_link_train(struct d
+       POSTING_READ(reg);
+       udelay(150);
+-      if (HAS_PCH_CPT(dev))
+-              cpt_phase_pointer_enable(dev, pipe);
+-
+       for (i = 0; i < 4; i++) {
+               reg = FDI_TX_CTL(pipe);
+               temp = I915_READ(reg);
+@@ -2593,9 +2578,6 @@ static void ivb_manual_fdi_link_train(st
+       POSTING_READ(reg);
+       udelay(150);
+-      if (HAS_PCH_CPT(dev))
+-              cpt_phase_pointer_enable(dev, pipe);
+-
+       for (i = 0; i < 4; i++) {
+               reg = FDI_TX_CTL(pipe);
+               temp = I915_READ(reg);
+@@ -2737,17 +2719,6 @@ static void ironlake_fdi_pll_disable(str
+       udelay(100);
+ }
+-static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+-{
+-      struct drm_i915_private *dev_priv = dev->dev_private;
+-      u32 flags = I915_READ(SOUTH_CHICKEN1);
+-
+-      flags &= ~(FDI_PHASE_SYNC_EN(pipe));
+-      I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
+-      flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
+-      I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
+-      POSTING_READ(SOUTH_CHICKEN1);
+-}
+ static void ironlake_fdi_disable(struct drm_crtc *crtc)
+ {
+       struct drm_device *dev = crtc->dev;
+@@ -2777,8 +2748,6 @@ static void ironlake_fdi_disable(struct
+               I915_WRITE(FDI_RX_CHICKEN(pipe),
+                          I915_READ(FDI_RX_CHICKEN(pipe) &
+                                    ~FDI_RX_PHASE_SYNC_POINTER_EN));
+-      } else if (HAS_PCH_CPT(dev)) {
+-              cpt_phase_pointer_disable(dev, pipe);
+       }
+       /* still set train pattern 1 */
index 450e59378a962005d84d68cd6b5dceb43c4ed23d..cd4f1b7abc13ae250715d51c05484cb628391293 100644 (file)
@@ -185,3 +185,4 @@ revert-mips-optimise-tlb-handlers-for-mips32-64-r2-cores.patch
 dm-thin-fix-race-between-simultaneous-io-and-discards-to-same-block.patch
 revert-rt2x00-don-t-let-mac80211-send-a-bar-when-an-ampdu-subframe-fails.patch
 edac-fix-kernel-panic-on-module-unloading.patch
+drm-i915-disable-cpt-phase-pointer-fdi-rx-workaround.patch