((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION <<
ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) {
/* driver request VRAM reservation for SR-IOV */
- adev->mman.drv_vram_usage_start_offset = (drv_start_addr &
- (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
- adev->mman.drv_vram_usage_size = drv_size << 10;
+ amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_DRV_VRAM_USAGE,
+ (drv_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10,
+ drv_size << 10, true);
}
*usage_bytes = 0;
memset(resv, 0, sizeof(*resv));
}
-/*
- * Driver Reservation functions
- */
-/**
- * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram
- *
- * @adev: amdgpu_device pointer
- *
- * free drv reserved vram if it has been reserved.
- */
-static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev)
-{
- amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo,
- NULL,
- &adev->mman.drv_vram_usage_va);
-}
-
-/**
- * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver
- *
- * @adev: amdgpu_device pointer
- *
- * create bo vram reservation from drv.
- */
-static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev)
-{
- u64 vram_size = adev->gmc.visible_vram_size;
-
- adev->mman.drv_vram_usage_va = NULL;
- adev->mman.drv_vram_usage_reserved_bo = NULL;
-
- if (adev->mman.drv_vram_usage_size == 0 ||
- adev->mman.drv_vram_usage_size > vram_size)
- return 0;
-
- return amdgpu_bo_create_kernel_at(adev,
- adev->mman.drv_vram_usage_start_offset,
- adev->mman.drv_vram_usage_size,
- &adev->mman.drv_vram_usage_reserved_bo,
- &adev->mman.drv_vram_usage_va);
-}
-
/*
* Memoy training reservation functions
*/
* The reserved VRAM for the driver must be pinned to a specific
* location in VRAM, so reserve it early.
*/
- r = amdgpu_ttm_drv_reserve_vram_init(adev);
- if (r)
- return r;
+ if (adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size >
+ adev->gmc.visible_vram_size) {
+ adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size = 0;
+ } else {
+ r = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE);
+ if (r)
+ return r;
+ }
/*
* only NAVI10 and later ASICs support IP discovery.
amdgpu_ttm_free_mmio_remap_bo(adev);
amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW_VRAM_USAGE);
- amdgpu_ttm_drv_reserve_vram_fini(adev);
+ amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE);
if (drm_dev_enter(adev_to_drm(adev), &idx)) {
bool keep_stolen_vga_memory;
- /* driver VRAM reservation */
- u64 drv_vram_usage_start_offset;
- u64 drv_vram_usage_size;
- struct amdgpu_bo *drv_vram_usage_reserved_bo;
- void *drv_vram_usage_va;
-
struct amdgpu_vram_resv resv_region[AMDGPU_RESV_MAX];
/* PAGE_SIZE'd BO for process memory r/w over SDMA. */
uint64_t retired_page;
uint32_t bp_idx, bp_cnt;
void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr;
- void *vram_usage_va = fw_va ? fw_va : adev->mman.drv_vram_usage_va;
+ void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr;
+ void *vram_usage_va = fw_va ? fw_va : drv_va;
memset(&bp, 0, sizeof(bp));
{
uint32_t *pfvf_data = NULL;
void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr;
+ void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr;
adev->virt.fw_reserve.p_pf2vf = NULL;
adev->virt.fw_reserve.p_vf2pf = NULL;
adev->virt.vf2pf_update_interval_ms = 0;
adev->virt.vf2pf_update_retry_cnt = 0;
- if (fw_va && adev->mman.drv_vram_usage_va) {
+ if (fw_va && drv_va) {
dev_warn(adev->dev, "Currently fw_vram and drv_vram should not have values at the same time!");
- } else if (fw_va || adev->mman.drv_vram_usage_va) {
+ } else if (fw_va || drv_va) {
/* go through this logic in ip_init and reset to init workqueue*/
amdgpu_virt_exchange_data(adev);
uint32_t bp_block_size = 0;
struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL;
void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr;
+ void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr;
- if (fw_va || adev->mman.drv_vram_usage_va) {
+ if (fw_va || drv_va) {
if (fw_va) {
if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) {
adev->virt.fw_reserve.p_pf2vf =
adev->virt.fw_reserve.ras_telemetry =
(fw_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10));
}
- } else if (adev->mman.drv_vram_usage_va) {
+ } else if (drv_va) {
adev->virt.fw_reserve.p_pf2vf =
(struct amd_sriov_msg_pf2vf_info_header *)
- (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10));
+ (drv_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10));
adev->virt.fw_reserve.p_vf2pf =
(struct amd_sriov_msg_vf2pf_info_header *)
- (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10));
+ (drv_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10));
adev->virt.fw_reserve.ras_telemetry =
- (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10));
+ (drv_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10));
}
amdgpu_virt_read_pf2vf_data(adev);
struct amdsriov_ras_telemetry *ras_telemetry_cpu;
struct amdsriov_ras_telemetry *ras_telemetry_gpu;
void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr;
+ void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr;
uint64_t fw_vram_usage_start_offset = 0;
uint64_t ras_telemetry_offset = 0;
fw_vram_usage_start_offset = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].offset;
ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry -
(uintptr_t)fw_va;
- } else if (adev->mman.drv_vram_usage_va &&
- adev->mman.drv_vram_usage_va <= adev->virt.fw_reserve.ras_telemetry) {
- fw_vram_usage_start_offset = adev->mman.drv_vram_usage_start_offset;
+ } else if (drv_va && drv_va <= adev->virt.fw_reserve.ras_telemetry) {
+ fw_vram_usage_start_offset = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].offset;
ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry -
- (uintptr_t)adev->mman.drv_vram_usage_va;
+ (uintptr_t)drv_va;
} else {
return -EINVAL;
}