#define AMDGPU_RAS_TYPE_VF 0x3
static int amdgpu_ras_query_interface_info(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd)
+ struct ras_cmd_ctx *cmd)
{
struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
struct ras_query_interface_info_rsp *output_data =
}
static int amdgpu_ras_get_devices_info(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd)
+ struct ras_cmd_ctx *cmd)
{
struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
struct ras_cmd_devices_info_rsp *output_data =
}
static int amdgpu_ras_inject_error(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
struct ras_cmd_inject_error_req *req =
}
static int amdgpu_ras_get_ras_safe_fb_addr_ranges(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct amdgpu_device *adev = (struct amdgpu_device *)ras_core->dev;
struct ras_cmd_dev_handle *input_data =
}
static int amdgpu_ras_translate_fb_address(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_translate_fb_address_req *req_buff =
(struct ras_cmd_translate_fb_address_req *)cmd->input_buff_raw;
{RAS_CMD__TRANSLATE_FB_ADDRESS, amdgpu_ras_translate_fb_address},
};
-int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ioctl *cmd, void *data)
+int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_func_map *ras_cmd = NULL;
int i, res;
int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core,
uint8_t *cmd_buf, uint32_t buf_size)
{
- struct ras_cmd_ioctl *cmd = (struct ras_cmd_ioctl *)cmd_buf;
+ struct ras_cmd_ctx *cmd = (struct ras_cmd_ctx *)cmd_buf;
struct ras_core_context *cmd_core = NULL;
struct ras_cmd_dev_handle *cmd_handle = NULL;
int timeout = 60;
};
int amdgpu_ras_handle_cmd(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data);
+ struct ras_cmd_ctx *cmd, void *data);
int amdgpu_ras_cmd_ioctl_handler(struct ras_core_context *ras_core,
uint8_t *cmd_buf, uint32_t buf_size);
}
static int ras_get_block_ecc_info(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_block_ecc_info_req *input_data =
(struct ras_cmd_block_ecc_info_req *)cmd->input_buff_raw;
}
static int ras_cmd_get_bad_pages(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_bad_pages_info_req *input_data =
(struct ras_cmd_bad_pages_info_req *)cmd->input_buff_raw;
}
static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))
return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
}
static int ras_cmd_reset_all_error_counts(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))
return RAS_CMD__ERROR_INVALID_INPUT_SIZE;
}
static int ras_cmd_get_cper_snapshot(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_cper_snapshot_rsp *output_data =
(struct ras_cmd_cper_snapshot_rsp *)cmd->output_buff_raw;
}
static int ras_cmd_get_cper_records(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_cper_record_req *req =
(struct ras_cmd_cper_record_req *)cmd->input_buff_raw;
}
static int ras_cmd_get_batch_trace_snapshot(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_batch_trace_snapshot_rsp *rsp =
(struct ras_cmd_batch_trace_snapshot_rsp *)cmd->output_buff_raw;
}
static int ras_cmd_get_batch_trace_records(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_batch_trace_record_req *input_data =
(struct ras_cmd_batch_trace_record_req *)cmd->input_buff_raw;
}
static int ras_cmd_inject_error(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_inject_error_req *req =
(struct ras_cmd_inject_error_req *)cmd->input_buff_raw;
};
int rascore_handle_cmd(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data)
+ struct ras_cmd_ctx *cmd, void *data)
{
struct ras_cmd_func_map *ras_cmd = NULL;
int i;
};
struct ras_core_context;
-struct ras_cmd_ioctl;
+struct ras_cmd_ctx;
struct ras_cmd_mgr {
struct list_head head;
struct ras_cmd_func_map {
uint32_t cmd_id;
int (*func)(struct ras_core_context *ras_core,
- struct ras_cmd_ioctl *cmd, void *data);
+ struct ras_cmd_ctx *cmd, void *data);
};
struct ras_device_bdf {
};
#pragma pack(push, 8)
-struct ras_cmd_ioctl {
+struct ras_cmd_ctx {
uint32_t magic;
union {
struct {
int ras_cmd_init(struct ras_core_context *ras_core);
int ras_cmd_fini(struct ras_core_context *ras_core);
-int rascore_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ioctl *cmd, void *data);
+int rascore_handle_cmd(struct ras_core_context *ras_core, struct ras_cmd_ctx *cmd, void *data);
uint64_t ras_cmd_get_dev_handle(struct ras_core_context *ras_core);
int ras_cmd_query_interface_info(struct ras_core_context *ras_core,
struct ras_query_interface_info_rsp *rsp);