spi: zynq_qspi: Fix the Rx FIFO overflow condition

Added the check for the Tx FIFO not empty condition
as well along with Rx FIFO not empty to get rid of
Rx FIFO overflow scenario.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 930ce363304afb4103c0f3b95c4f7fad082c7faa..2fa984d3bfb1aa84f66a8c87a4e2eec83c0246ad 100644 (file)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -575,27 +575,32 @@ static int zynq_qspi_irq_poll(struct zynq_qspi *zqspi)
                 * is empty
                 */
                u32 config_reg;
-
-               /* Read out the data from the RX FIFO */
-               while (readl(&zynq_qspi_base->isr) &
-                               ZYNQ_QSPI_IXR_RXNEMTY_MASK) {
-                       u32 data;
-
-                       data = readl(&zynq_qspi_base->drxr);
-
-                       if ((zqspi->inst_response) &&
-                           (!((zqspi->curr_inst->opcode ==
-                               ZYNQ_QSPI_FLASH_OPCODE_RDSR1) ||
-                              (zqspi->curr_inst->opcode ==
-                               ZYNQ_QSPI_FLASH_OPCODE_RDSR2)))) {
-                               zqspi->inst_response = 0;
-                               zynq_qspi_copy_read_data(zqspi, data,
+               while (!(readl(&zynq_qspi_base->isr) &
+                       ZYNQ_QSPI_IXR_TXNFULL_MASK) ||
+                       (readl(&zynq_qspi_base->isr) &
+                       ZYNQ_QSPI_IXR_RXNEMTY_MASK)) {
+                       /* Read out the data from the RX FIFO */
+                       while (readl(&zynq_qspi_base->isr) &
+                                       ZYNQ_QSPI_IXR_RXNEMTY_MASK) {
+                               u32 data;
+
+                               data = readl(&zynq_qspi_base->drxr);
+
+                               if ((zqspi->inst_response) &&
+                                   (!((zqspi->curr_inst->opcode ==
+                                   ZYNQ_QSPI_FLASH_OPCODE_RDSR1) ||
+                                   (zqspi->curr_inst->opcode ==
+                                   ZYNQ_QSPI_FLASH_OPCODE_RDSR2)))) {
+                                       zqspi->inst_response = 0;
+                                       zynq_qspi_copy_read_data(zqspi, data,
                                                zqspi->curr_inst->inst_size);
-                       } else if (zqspi->bytes_to_receive < 4) {
-                               zynq_qspi_copy_read_data(zqspi, data,
-                                                      zqspi->bytes_to_receive);
-                       } else {
-                               zynq_qspi_copy_read_data(zqspi, data, 4);
+                               } else if (zqspi->bytes_to_receive < 4) {
+                                       zynq_qspi_copy_read_data(zqspi, data,
+                                               zqspi->bytes_to_receive);
+                               } else {
+                                       zynq_qspi_copy_read_data(zqspi, data,
+                                                               4);
+                               }
                        }
                }