--- /dev/null
+From 0d8247f91470d67eb90981e82174d83cf1451490 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 13 Jan 2022 16:48:51 +0200
+Subject: ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency
+
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+
+[ Upstream commit dc3005703f8cd893d325081c20b400e08377d9bb ]
+
+Remove CONFIG_SOC_SAMA7 dependency to avoid having #ifdef preprocessor
+directives in driver code (arch/arm/mach-at91/pm.c). This prepares the
+code for next commits.
+
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
+Link: https://lore.kernel.org/r/20220113144900.906370-2-claudiu.beznea@microchip.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/soc/at91/sama7-ddr.h | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h
+index 72d19887ab810..f203f34dba12e 100644
+--- a/include/soc/at91/sama7-ddr.h
++++ b/include/soc/at91/sama7-ddr.h
+@@ -11,8 +11,6 @@
+ #ifndef __SAMA7_DDR_H__
+ #define __SAMA7_DDR_H__
+
+-#ifdef CONFIG_SOC_SAMA7
+-
+ /* DDR3PHY */
+ #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
+ #define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
+@@ -83,6 +81,4 @@
+ #define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */
+ #define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */
+
+-#endif /* CONFIG_SOC_SAMA7 */
+-
+ #endif /* __SAMA7_DDR_H__ */
+--
+2.35.1
+