backport: re PR target/80510 (Optimize Power7/power8 Altivec load/stores)

[gcc]
2017-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	Backport from mainline
	2017-06-23  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/80510
	* config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in
	32-bit, since indexed is not valid for DImode.
	(mov<mode>_hardfloat32): Reorder ISA 2.07 load/stores before ISA
	3.0 d-form load/stores to be the same as mov<mode>_hardfloat64.
	(define_peephole2 for Altivec d-form load): Add 32-bit support.
	(define_peephole2 for Altivec d-form store): Likewise.

[gcc/testsuite]
2017-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	Backport from mainline
	2017-06-23  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/80510
	* gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit.
	* gcc.target/powerpc/pr80510-2.c: Likewise.

From-SVN: r249836

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 101e86e30bf3f6a4b44a4cd81913a03ff7059578..9ad493b0794caf0d7fb6b01c997b0c569e73f280 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2017-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       Backport from mainline
+       2017-06-23  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/80510
+       * config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in
+       32-bit, since indexed is not valid for DImode.
+       (mov<mode>_hardfloat32): Reorder ISA 2.07 load/stores before ISA
+       3.0 d-form load/stores to be the same as mov<mode>_hardfloat64.
+       (define_peephole2 for Altivec d-form load): Add 32-bit support.
+       (define_peephole2 for Altivec d-form store): Likewise.
+
 2017-06-27  Segher Boessenkool  <segher@kernel.crashing.org>
 
        Backports from trunk:

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a16d8a29d261acfca2a9f5f5cf7f7b1d6037a0a7..ede5306a1f38518e18b1822b3e22b681e339a47e 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6750,8 +6750,8 @@
 ;; except for 0.0 which can be created on VSX with an xor instruction.
 
 (define_insn "*mov<mode>_hardfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,o,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
-       (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,o,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
+       (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -6759,10 +6759,10 @@
    stfd%U0%X0 %1,%0
    lfd%U1%X1 %0,%1
    fmr %0,%1
-   lxsd%U1x %x0,%y1
-   stxsd%U0x %x1,%y0
    lxsd %0,%1
    stxsd %1,%0
+   lxsd%U1x %x0,%y1
+   stxsd%U0x %x1,%y0
    xxlor %x0,%x1,%x1
    xxlxor %x0,%x0,%x0
    #
@@ -13180,13 +13180,13 @@
 ;;     move fpr->altivec
 
 (define_peephole2
-  [(match_scratch:DI 0 "b")
+  [(match_scratch:P 0 "b")
    (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
        (match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
    (set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
        (match_dup 1))]
-  "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
-   && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
+  "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
+   && peep2_reg_dead_p (2, operands[1])"
   [(set (match_dup 0)
        (match_dup 4))
    (set (match_dup 3)
@@ -13201,7 +13201,7 @@
   add_op0 = XEXP (addr, 0);
   add_op1 = XEXP (addr, 1);
   gcc_assert (REG_P (add_op0));
-  new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
+  new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
 
   operands[4] = add_op1;
   operands[5] = change_address (mem, <MODE>mode, new_addr);
@@ -13213,13 +13213,13 @@
 ;;     store fpr
 
 (define_peephole2
-  [(match_scratch:DI 0 "b")
+  [(match_scratch:P 0 "b")
    (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
        (match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
    (set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
        (match_dup 1))]
-  "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
-   && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
+  "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
+   && peep2_reg_dead_p (2, operands[1])"
   [(set (match_dup 0)
        (match_dup 4))
    (set (match_dup 5)
@@ -13234,7 +13234,7 @@
   add_op0 = XEXP (addr, 0);
   add_op1 = XEXP (addr, 1);
   gcc_assert (REG_P (add_op0));
-  new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
+  new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
 
   operands[4] = add_op1;
   operands[5] = change_address (mem, <MODE>mode, new_addr);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3a2cc0a018aacd6f2aa491a82871f5b15e884777..0ebf4f47aa09837a973ed824d61bcded29b8e5eb 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2017-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       Backport from mainline
+       2017-06-23  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/80510
+       * gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit.
+       * gcc.target/powerpc/pr80510-2.c: Likewise.
+
 2017-06-27  Segher Boessenkool  <segher@kernel.crashing.org>
 
        Backports from trunk:

diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c
index f9d9fde49e5d81aac5577ed1192671a4a3f62e00..deb51ac9916686ec5c20ad88bdbe93e524048e7c 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr80510-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80510-1.c
@@ -1,14 +1,12 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_vsx_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
 /* { dg-options "-mcpu=power7 -O2" } */
 
 /* Make sure that STXSDX is generated for double scalars in Altivec registers
    on power7 instead of moving the value to a FPR register and doing a X-FORM
-   store.
-
-   32-bit currently does not have support for STXSDX in the mov{df,dd} patterns.  */
+   store.  */
 
 #ifndef TYPE
 #define TYPE double

diff --git a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c
index 6edcc36e065b9cf3ba78f8297c264c691161af1f..b4d2491551bfa2af758cf560fa817e7b79dce0c2 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr80510-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr80510-2.c
@@ -1,14 +1,12 @@
-/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } } */
 /* { dg-require-effective-target powerpc_p8vector_ok } */
 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
 /* { dg-options "-mcpu=power8 -O2" } */
 
 /* Make sure that STXSSPX is generated for float scalars in Altivec registers
    on power7 instead of moving the value to a FPR register and doing a X-FORM
-   store.
-
-   32-bit currently does not have support for STXSSPX in the mov{sf,sd} patterns.  */
+   store.  */
 
 #ifndef TYPE
 #define TYPE float