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dts: sophgo: sg2042: added numa id description
authorHan Gao <rabenda.cn@gmail.com>
Wed, 10 Sep 2025 10:55:31 +0000 (18:55 +0800)
committerInochi Amaoto <inochiama@gmail.com>
Wed, 17 Sep 2025 06:36:19 +0000 (14:36 +0800)
According to the description of [1], sg2042 is divided into 4 numa.
STREAM test performance will improve.

Before:
Function    Best Rate MB/s  Avg time     Min time     Max time
Copy:           10739.7     0.015687     0.014898     0.016385
Scale:          10865.9     0.015628     0.014725     0.016757
Add:            10622.3     0.023276     0.022594     0.023899
Triad:          10583.4     0.023653     0.022677     0.024761

After:
Function    Best Rate MB/s  Avg time     Min time     Max time
Copy:           34254.9     0.005142     0.004671     0.005995
Scale:          37735.5     0.004752     0.004240     0.005407
Add:            44206.8     0.005983     0.005429     0.006461
Triad:          43040.6     0.006320     0.005576     0.006996

[1] https://github.com/sophgo/sophgo-doc/blob/main/SG2042/TRM/source/pic/mesh.png

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20250910105531.519897-1-rabenda.cn@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi patch | blob | blame | history
arch/riscv/boot/dts/sophgo/sg2042.dtsi patch | blob | blame | history

diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index 77ded53042728277e9084ffc80d054a975b25368..94a4b71acad320e32bdad8638cdeaacf846b8cb3 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -272,6 +272,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache0>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu0_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -299,6 +300,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache0>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu1_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -326,6 +328,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache0>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu2_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -353,6 +356,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache0>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu3_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -380,6 +384,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache1>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu4_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -407,6 +412,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache1>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu5_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -434,6 +440,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache1>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu6_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -461,6 +468,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache1>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu7_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -488,6 +496,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache4>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu8_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -515,6 +524,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache4>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu9_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -542,6 +552,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache4>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu10_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -569,6 +580,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache4>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu11_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -596,6 +608,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache5>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu12_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -623,6 +636,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache5>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu13_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -650,6 +664,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache5>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu14_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -677,6 +692,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache5>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu15_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -704,6 +720,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache2>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu16_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -731,6 +748,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache2>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu17_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -758,6 +776,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache2>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu18_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -785,6 +804,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache2>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu19_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -812,6 +832,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache3>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu20_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -839,6 +860,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache3>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu21_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -866,6 +888,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache3>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu22_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -893,6 +916,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache3>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <0>;
 
                        cpu23_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -920,6 +944,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache6>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu24_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -947,6 +972,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache6>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu25_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -974,6 +1000,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache6>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu26_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1001,6 +1028,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache6>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu27_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1028,6 +1056,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache7>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu28_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1055,6 +1084,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache7>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu29_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1082,6 +1112,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache7>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu30_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1109,6 +1140,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache7>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <1>;
 
                        cpu31_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1136,6 +1168,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache8>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu32_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1163,6 +1196,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache8>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu33_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1190,6 +1224,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache8>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu34_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1217,6 +1252,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache8>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu35_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1244,6 +1280,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache9>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu36_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1271,6 +1308,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache9>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu37_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1298,6 +1336,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache9>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu38_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1325,6 +1364,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache9>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu39_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1352,6 +1392,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache12>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu40_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1379,6 +1420,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache12>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu41_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1406,6 +1448,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache12>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu42_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1433,6 +1476,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache12>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu43_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1460,6 +1504,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache13>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu44_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1487,6 +1532,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache13>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu45_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1514,6 +1560,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache13>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu46_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1541,6 +1588,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache13>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu47_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1568,6 +1616,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache10>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu48_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1595,6 +1644,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache10>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu49_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1622,6 +1672,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache10>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu50_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1649,6 +1700,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache10>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu51_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1676,6 +1728,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache11>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu52_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1703,6 +1756,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache11>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu53_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1730,6 +1784,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache11>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu54_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1757,6 +1812,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache11>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <2>;
 
                        cpu55_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1784,6 +1840,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache14>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu56_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1811,6 +1868,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache14>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu57_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1838,6 +1896,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache14>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu58_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1865,6 +1924,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache14>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu59_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1892,6 +1952,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache15>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu60_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1919,6 +1980,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache15>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu61_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1946,6 +2008,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache15>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu62_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
@@ -1973,6 +2036,7 @@
                        d-cache-sets = <512>;
                        next-level-cache = <&l2_cache15>;
                        mmu-type = "riscv,sv39";
+                       numa-node-id = <3>;
 
                        cpu63_intc: interrupt-controller {
                                compatible = "riscv,cpu-intc";
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index b3e4d3c18fdcf94c2294a56ed6ad866fc59a6adb..029561b6ad8130e4943001bf44e36087b75c2708 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -19,6 +19,26 @@
        #size-cells = <2>;
        dma-noncoherent;
 
+       distance-map {
+               compatible = "numa-distance-map-v1";
+               distance-matrix = <0 0 10>,
+                                 <0 1 15>,
+                                 <0 2 25>,
+                                 <0 3 30>,
+                                 <1 0 15>,
+                                 <1 1 10>,
+                                 <1 2 30>,
+                                 <1 3 25>,
+                                 <2 0 25>,
+                                 <2 1 30>,
+                                 <2 2 10>,
+                                 <2 3 15>,
+                                 <3 0 30>,
+                                 <3 1 25>,
+                                 <3 2 15>,
+                                 <3 3 10>;
+       };
+
        aliases {
                serial0 = &uart0;
        };
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