xilinx_axienet: pump events as appropriate

When the conditions blocking receiving are cleared, check for buffered rx
packets.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index 578529022418a8e440698b3f09ed62f8d748304a..07c4badd989d74489ca2e1b51f4bff91259b6cc5 100644 (file)
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -516,6 +516,8 @@ static void enet_write(void *opaque, hwaddr addr,
             s->rcw[addr & 1] = value;
             if ((addr & 1) && value & RCW1_RST) {
                 axienet_rx_reset(s);
+            } else {
+                qemu_flush_queued_packets(qemu_get_queue(s->nic));
             }
             break;