clk: eyeq: Add Mobileye EyeQ6Lplus OLB

Declare the PLLs and fixed factors found in the EyeQ6Lplus OLB as part
of the match data for the "mobileye,eyeq6lplus-olb" compatible.

The PLL and fixed factor of the CPU are registered in early init as they
are required during the boot by the GIC timer.

Also select clk-eyeq for all EYEQ SoCs instead of listing each one
individually, as it is needed by all Mobileye EyeQ SoC.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3d803b4cf5c13d82ae936eb87ba1c225fa2ab8ce..240e9dbeff2b1aade5c8f6cb00d6cc17fdccf525 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -236,9 +236,9 @@ config COMMON_CLK_EP93XX
 
 config COMMON_CLK_EYEQ
        bool "Clock driver for the Mobileye EyeQ platform"
-       depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
+       depends on EYEQ || COMPILE_TEST
        select AUXILIARY_BUS
-       default MACH_EYEQ5 || MACH_EYEQ6H
+       default EYEQ
        help
          This driver provides clocks found on Mobileye EyeQ5, EyeQ6L and Eye6H
          SoCs. Controllers live in shared register regions called OLB. Driver

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 11df9f167b5960c02156c7606f58b330ef7ec4ed..c1dccedf8d5b1f04b55d7ce230bdd8832eebe82d 100644 (file)
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -45,6 +45,7 @@
 #include <linux/types.h>
 
 #include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
 
 /* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
 #define PCSR0_DAC_EN                   BIT(0)
@@ -571,6 +572,68 @@ static const struct eqc_match_data eqc_eyeq6l_match_data = {
        .reset_auxdev_name = "reset",
 };
 
+static const struct eqc_pll eqc_eyeq6lplus_early_plls[] = {
+       { .index = EQ6LPC_PLL_CPU, .name = "pll-cpu", .reg64 = 0x058 },
+};
+
+static const struct eqc_pll eqc_eyeq6lplus_plls[] = {
+       { .index = EQ6LPC_PLL_DDR, .name = "pll-ddr", .reg64 = 0x02C },
+       { .index = EQ6LPC_PLL_ACC, .name = "pll-acc", .reg64 = 0x034 },
+       { .index = EQ6LPC_PLL_PER, .name = "pll-per", .reg64 = 0x03C },
+       { .index = EQ6LPC_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq6lplus_early_fixed_factors[] = {
+       { EQ6LPC_CPU_OCC,       "occ-cpu",      1, 1,   EQ6LPC_PLL_CPU },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq6lplus_fixed_factors[] = {
+       { EQ6LPC_DDR_OCC,       "occ-ddr",      1, 1,   EQ6LPC_PLL_DDR },
+
+       { EQ6LPC_ACC_VDI,       "vdi-div",      1, 10,  EQ6LPC_PLL_ACC },
+       { EQ6LPC_ACC_OCC,       "occ-acc",      1, 1,   EQ6LPC_PLL_ACC },
+       { EQ6LPC_ACC_FCMU,      "fcmu-a-clk",   1, 10,  EQ6LPC_ACC_OCC },
+
+       { EQ6LPC_PER_OCC,       "occ-per",      1, 1,   EQ6LPC_PLL_PER },
+       { EQ6LPC_PER_I2C_SER,   "i2c-ser-clk",  1, 10,  EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_PCLK,      "pclk",         1, 4,   EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_TSU,       "tsu-clk",      1, 8,   EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_OSPI,      "ospi-ref-clk", 1, 10,  EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_GPIO,      "gpio-clk",     1, 4,   EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_TIMER,     "timer-clk",    1, 4,   EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_I2C,       "i2c-clk",      1, 4,   EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_UART,      "uart-clk",     1, 4,   EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_SPI,       "spi-clk",      1, 4,   EQ6LPC_PER_OCC },
+       { EQ6LPC_PER_PERIPH,    "periph-clk",   1, 1,   EQ6LPC_PER_OCC },
+
+       { EQ6LPC_VDI_OCC,       "occ-vdi",      1, 1,   EQ6LPC_PLL_VDI },
+};
+
+static const struct eqc_early_match_data eqc_eyeq6lplus_early_match_data __initconst = {
+       .early_pll_count        = ARRAY_SIZE(eqc_eyeq6lplus_early_plls),
+       .early_plls             = eqc_eyeq6lplus_early_plls,
+
+       .early_fixed_factor_count       = ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors),
+       .early_fixed_factors            = eqc_eyeq6lplus_early_fixed_factors,
+
+       .late_clk_count         = ARRAY_SIZE(eqc_eyeq6lplus_plls) +
+       ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors),
+};
+
+static const struct eqc_match_data eqc_eyeq6lplus_match_data = {
+       .pll_count      = ARRAY_SIZE(eqc_eyeq6lplus_plls),
+       .plls           = eqc_eyeq6lplus_plls,
+
+       .fixed_factor_count     = ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors),
+       .fixed_factors          = eqc_eyeq6lplus_fixed_factors,
+
+       .reset_auxdev_name = "reset",
+       .pinctrl_auxdev_name = "pinctrl",
+
+       .early_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_early_plls) +
+       ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors),
+};
+
 static const struct eqc_match_data eqc_eyeq6h_west_match_data = {
        .reset_auxdev_name = "reset_west",
 };
@@ -672,6 +735,7 @@ static const struct eqc_match_data eqc_eyeq6h_acc_match_data = {
 static const struct of_device_id eqc_match_table[] = {
        { .compatible = "mobileye,eyeq5-olb", .data = &eqc_eyeq5_match_data },
        { .compatible = "mobileye,eyeq6l-olb", .data = &eqc_eyeq6l_match_data },
+       { .compatible = "mobileye,eyeq6lplus-olb", .data = &eqc_eyeq6lplus_match_data },
        { .compatible = "mobileye,eyeq6h-west-olb", .data = &eqc_eyeq6h_west_match_data },
        { .compatible = "mobileye,eyeq6h-east-olb", .data = &eqc_eyeq6h_east_match_data },
        { .compatible = "mobileye,eyeq6h-south-olb", .data = &eqc_eyeq6h_south_match_data },
@@ -855,3 +919,9 @@ static void __init eqc_eyeq6h_west_early_init(struct device_node *np)
 }
 CLK_OF_DECLARE_DRIVER(eqc_eyeq6h_west, "mobileye,eyeq6h-west-olb",
                      eqc_eyeq6h_west_early_init);
+
+static void __init eqc_eyeq6lplus_early_init(struct device_node *np)
+{
+       eqc_early_init(np, &eqc_eyeq6lplus_early_match_data);
+}
+CLK_OF_DECLARE_DRIVER(eqc_eyeq6lplus, "mobileye,eyeq6lplus-olb", eqc_eyeq6lplus_early_init);