armv8: Sync mmu_set_region_dcache_behaviour() with mainline

Based on our submission sync code with mainline.
Mainline patch:
"armv8: caches: Added routine to set non cacheable region"
(sha1: dad17fd51027ad02ac8f02deed186d08109d61fd)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 25a2136a3cdf55e855efc014291a4ed43a117232..bddcdf714a31747d26a3d2593ea3535d4dc65d9b 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -139,13 +139,21 @@ int dcache_status(void)
        return (get_sctlr() & CR_C) != 0;
 }
 
+u64 *__weak arch_get_page_table(void) {
+       puts("No page table offset defined\n");
+
+       return NULL;
+}
+
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
                                     enum dcache_option option)
 {
-       /* get the level2_table0 start address */
-       u64 *page_table = (u64 *)(gd->arch.tlb_addr + 0x3000);
+       u64 *page_table = arch_get_page_table();
        u64 upto, end;
 
+       if (page_table == NULL)
+               return;
+
        end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
              MMU_SECTION_SHIFT;
        start = start >> MMU_SECTION_SHIFT;
@@ -153,9 +161,14 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
                page_table[upto] &= ~PMD_ATTRINDX_MASK;
                page_table[upto] |= PMD_ATTRINDX(option);
        }
-
-       flush_dcache_range(page_table[start], page_table[end]);
+       asm volatile("dsb sy");
        __asm_invalidate_tlb_all();
+       asm volatile("dsb sy");
+       asm volatile("isb");
+       start = start << MMU_SECTION_SHIFT;
+       end = end << MMU_SECTION_SHIFT;
+       flush_dcache_range(start, end);
+       asm volatile("dsb sy");
 }
 #else  /* CONFIG_SYS_DCACHE_OFF */
 

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index c88687860ec14bcaa0d3878c2c9954c10e6b02a4..b0cf6d9fb7e80825120dc9665f76098ebc7794d0 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -15,7 +15,7 @@
 #define CR_EE          (1 << 25)       /* Exception (Big) Endian       */
 
 #define PGTABLE_SIZE   (0x10000)
-/* 2M granularity */
+/* 2MB granularity */
 #define MMU_SECTION_SHIFT      21
 
 #ifndef __ASSEMBLY__