clk: zynqmp: enable topsw_lsbus clock

Display port is using topsw_lsbus clock, it is failing
while enabling the clock, so enable the topsw_lsbus clock.

Signed-off-by: Sreekanth Sunnam <sreekanth.sunnam@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20231204084515.9488-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 1cfe0e25b1052bae2644f0aaf75d177d9c708fb0..c059b9e8e65994fd9344bb4b468964ec199b7b39 100644 (file)
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -844,6 +844,7 @@ static int zynqmp_clk_enable(struct clk *clk)
                break;
        case qspi_ref ... can1_ref:
        case lpd_lsbus:
+       case topsw_lsbus:
                clkact_shift = 24;
                mask = 0x1;
                break;