arm64: dts: qcom: sm8550: add PPI interrupt partitions for the ARM PMUs

The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper
interrupt partition maps and use the 4th interrupt cell to pass the
partition phandle for each ARM PMU node.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-2-a8915672e996@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 2ebe02e2ca8c03ac9b987af720c7ebe1cd63afec..1b7fbbdba2df986e1efca5dbfa36c01eb1be0836 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -399,22 +399,22 @@
 
        pmu-a510 {
                compatible = "arm,cortex-a510-pmu";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
        };
 
        pmu-a710 {
                compatible = "arm,cortex-a710-pmu";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
        };
 
        pmu-a715 {
                compatible = "arm,cortex-a715-pmu";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster2>;
        };
 
        pmu-x3 {
                compatible = "arm,cortex-x3-pmu";
-               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster3>;
        };
 
        psci {
@@ -5066,6 +5066,24 @@
                        #address-cells = <2>;
                        #size-cells = <2>;
 
+                       ppi-partitions {
+                               ppi_cluster0: interrupt-partition-0 {
+                                       affinity = <&cpu0 &cpu1 &cpu2>;
+                               };
+
+                               ppi_cluster1: interrupt-partition-1 {
+                                       affinity = <&cpu3 &cpu4>;
+                               };
+
+                               ppi_cluster2: interrupt-partition-2 {
+                                       affinity = <&cpu5 &cpu6>;
+                               };
+
+                               ppi_cluster3: interrupt-partition-3 {
+                                       affinity = <&cpu7>;
+                               };
+                       };
+
                        gic_its: msi-controller@17140000 {
                                compatible = "arm,gic-v3-its";
                                reg = <0 0x17140000 0 0x20000>;