powerpc/perf: Fix SDAR_MODE value for continous sampling on Power9

commit 20dd4c624d25156d5ec3345bbb690b98175ef879 upstream.

In case of continous sampling (non-marked), the code currently
sets MMCRA[SDAR_MODE] to 0b01 (Update on TLB miss) for Power9 DD1.

On DD2 and later it copies the sdar_mode value from the event code,
which for most events is 0b00 (No updates).

However we must set a non-zero value for SDAR_MODE when doing
continuous sampling, so honor the event code, unless it's zero, in
which case we use use 0b01 (Update on TLB miss).

Fixes: 78b4416aa249 ("powerpc/perf: Handle sdar_mode for marked event in power9")
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 8125160be7bc34c77e4583296c6d4bc1fafe816c..3f3aa9a7063ab32acfd71dec1b04d973e6d7394b 100644 (file)
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -90,13 +90,15 @@ static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
         *      MMCRA[SDAR_MODE] will be set to 0b01
         * For rest
         *      MMCRA[SDAR_MODE] will be set from event code.
+        *      If sdar_mode from event is zero, default to 0b01. Hardware
+        *      requires that we set a non-zero value.
         */
        if (cpu_has_feature(CPU_FTR_ARCH_300)) {
                if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
                        *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
-               else if (!cpu_has_feature(CPU_FTR_POWER9_DD1))
+               else if (!cpu_has_feature(CPU_FTR_POWER9_DD1) && p9_SDAR_MODE(event))
                        *mmcra |=  p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT;
-               else if (cpu_has_feature(CPU_FTR_POWER9_DD1))
+               else
                        *mmcra |= MMCRA_SDAR_MODE_TLB;
        } else
                *mmcra |= MMCRA_SDAR_MODE_TLB;