]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
cxl: Add helper to detect top of CXL device topology
authorDave Jiang <dave.jiang@intel.com>
Fri, 29 Aug 2025 18:09:19 +0000 (11:09 -0700)
committerDave Jiang <dave.jiang@intel.com>
Wed, 17 Sep 2025 15:49:50 +0000 (08:49 -0700)
Add a helper to replace the open code detection of CXL device hierarchy
root, or the host bridge. The helper will be used for delayed downstream
port (dport) creation.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Robert Richter <rrichter@amd.com>
Tested-by: Robert Richter <rrichter@amd.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
drivers/cxl/core/port.c

index 29197376b18e37144a4785c68511eb4490822061..855623cebd7d0ce0b08e223a8f39009f400330fc 100644 (file)
 static DEFINE_IDA(cxl_port_ida);
 static DEFINE_XARRAY(cxl_root_buses);
 
+/*
+ * The terminal device in PCI is NULL and @platform_bus
+ * for platform devices (for cxl_test)
+ */
+static bool is_cxl_host_bridge(struct device *dev)
+{
+       return (!dev || dev == &platform_bus);
+}
+
 int cxl_num_decoders_committed(struct cxl_port *port)
 {
        lockdep_assert_held(&cxl_rwsem.region);
@@ -1541,7 +1550,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd,
        resource_size_t component_reg_phys;
        int rc;
 
-       if (!dparent) {
+       if (is_cxl_host_bridge(dparent)) {
                /*
                 * The iteration reached the topology root without finding the
                 * CXL-root 'cxl_port' on a previous iteration, fail for now to
@@ -1629,11 +1638,7 @@ retry:
                struct device *uport_dev;
                struct cxl_dport *dport;
 
-               /*
-                * The terminal "grandparent" in PCI is NULL and @platform_bus
-                * for platform devices
-                */
-               if (!dport_dev || dport_dev == &platform_bus)
+               if (is_cxl_host_bridge(dport_dev))
                        return 0;
 
                uport_dev = dport_dev->parent;