(set_attr "timings" "11,11,11,11,11,33")]
)
-(define_insn "smin<int_modes:mode>3"
- [(set (match_operand:int_modes 0 "register_operand" "=r,r,r,r,r,r")
- (smin:int_modes (match_operand:int_modes 1 "register_operand" "%0,0,0,0,0,0")
- (match_operand:int_modes 2 "rx_source_operand"
- "r,Sint08,Sint16,Sint24,i,Q")))]
+(define_insn "sminsi3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
+ (smin:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
+ (match_operand:SI 2 "rx_source_operand"
+ "r,Sint08,Sint16,Sint24,i,Q")))]
""
"min\t%Q2, %0"
[(set_attr "length" "3,4,5,6,7,6")