drm/i915/cx0: Replace XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US with XELPDP_PORT_POWERD...

There was a completely unjustified change to the cx0 powerdown
timeout, and the way it was done now prevents future conversion
to poll_timeout_us().

Assuming there was some reason the bigger timeout let's nuke
the old short timeout (XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US)
nd replace it with the bigger timeout
(XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS).

For consistency with intel_wait_for_register() we'll stick to the
default 2 usec for the fast timeout.

v2: Go for the longer (ms) timeout in case it actually matters
v3: Note the defaullt 2 usec fast timeout (Jani)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251106152049.21115-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index ddc26e383714140921d2980d150891f1af17b495..e8a96a60fdd651daa3bf2ba29726e3c24df10f65 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2830,7 +2830,7 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
        /* Update Timeout Value */
        if (intel_de_wait_custom(display, buf_ctl2_reg,
                                 intel_cx0_get_powerdown_update(lane_mask), 0,
-                                XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 2, NULL))
+                                2, XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
                drm_warn(display->drm,
                         "PHY %c failed to bring out of lane reset\n",
                         phy_name(phy));

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 635b35669348c1073d5e2aeb4a8a1eddbc7514d3..62db0fd99f4a525af280832a01fd68a4db2d9c13 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -80,7 +80,7 @@
 #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US             20
 #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US           100
 #define XELPDP_PORT_RESET_START_TIMEOUT_US             5
-#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US                100
+#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS                2
 #define XELPDP_PORT_RESET_END_TIMEOUT                  15
 #define XELPDP_REFCLK_ENABLE_TIMEOUT_US                        1