--- /dev/null
+From foo@baz Sat Dec 19 01:44:26 PM CET 2020
+From: Fangrui Song <maskray@google.com>
+Date: Thu, 29 Oct 2020 11:19:51 -0700
+Subject: arm64: Change .weak to SYM_FUNC_START_WEAK_PI for arch/arm64/lib/mem*.S
+
+From: Fangrui Song <maskray@google.com>
+
+commit ec9d78070de986ecf581ea204fd322af4d2477ec upstream.
+
+Commit 39d114ddc682 ("arm64: add KASAN support") added .weak directives to
+arch/arm64/lib/mem*.S instead of changing the existing SYM_FUNC_START_PI
+macros. This can lead to the assembly snippet `.weak memcpy ... .globl
+memcpy` which will produce a STB_WEAK memcpy with GNU as but STB_GLOBAL
+memcpy with LLVM's integrated assembler before LLVM 12. LLVM 12 (since
+https://reviews.llvm.org/D90108) will error on such an overridden symbol
+binding.
+
+Use the appropriate SYM_FUNC_START_WEAK_PI instead.
+
+Fixes: 39d114ddc682 ("arm64: add KASAN support")
+Reported-by: Sami Tolvanen <samitolvanen@google.com>
+Signed-off-by: Fangrui Song <maskray@google.com>
+Tested-by: Sami Tolvanen <samitolvanen@google.com>
+Tested-by: Nick Desaulniers <ndesaulniers@google.com>
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Cc: <stable@vger.kernel.org>
+Link: https://lore.kernel.org/r/20201029181951.1866093-1-maskray@google.com
+Signed-off-by: Will Deacon <will@kernel.org>
+[nd: backport to adjust for missing:
+ commit 3ac0f4526dfb ("arm64: lib: Use modern annotations for assembly functions")
+ commit 35e61c77ef38 ("arm64: asm: Add new-style position independent function annotations")]
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/lib/memcpy.S | 3 +--
+ arch/arm64/lib/memmove.S | 3 +--
+ arch/arm64/lib/memset.S | 3 +--
+ 3 files changed, 3 insertions(+), 6 deletions(-)
+
+--- a/arch/arm64/lib/memcpy.S
++++ b/arch/arm64/lib/memcpy.S
+@@ -68,9 +68,8 @@
+ stp \ptr, \regB, [\regC], \val
+ .endm
+
+- .weak memcpy
+ ENTRY(__memcpy)
+-ENTRY(memcpy)
++WEAK(memcpy)
+ #include "copy_template.S"
+ ret
+ ENDPIPROC(memcpy)
+--- a/arch/arm64/lib/memmove.S
++++ b/arch/arm64/lib/memmove.S
+@@ -57,9 +57,8 @@ C_h .req x12
+ D_l .req x13
+ D_h .req x14
+
+- .weak memmove
+ ENTRY(__memmove)
+-ENTRY(memmove)
++WEAK(memmove)
+ cmp dstin, src
+ b.lo __memcpy
+ add tmp1, src, count
+--- a/arch/arm64/lib/memset.S
++++ b/arch/arm64/lib/memset.S
+@@ -54,9 +54,8 @@ dst .req x8
+ tmp3w .req w9
+ tmp3 .req x9
+
+- .weak memset
+ ENTRY(__memset)
+-ENTRY(memset)
++WEAK(memset)
+ mov dst, dstin /* Preserve return value. */
+ and A_lw, val, #255
+ orr A_lw, A_lw, A_lw, lsl #8
--- /dev/null
+From foo@baz Sat Dec 19 01:43:35 PM CET 2020
+From: Sami Tolvanen <samitolvanen@google.com>
+Date: Thu, 31 Oct 2019 12:57:05 -0700
+Subject: arm64: lse: fix LSE atomics with LLVM's integrated assembler
+
+From: Sami Tolvanen <samitolvanen@google.com>
+
+commit e0d5896bd356cd577f9710a02d7a474cdf58426b upstream.
+
+Unlike gcc, clang considers each inline assembly block to be independent
+and therefore, when using the integrated assembler for inline assembly,
+any preambles that enable features must be repeated in each block.
+
+This change defines __LSE_PREAMBLE and adds it to each inline assembly
+block that has LSE instructions, which allows them to be compiled also
+with clang's assembler.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/671
+Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
+Tested-by: Andrew Murray <andrew.murray@arm.com>
+Tested-by: Kees Cook <keescook@chromium.org>
+Reviewed-by: Andrew Murray <andrew.murray@arm.com>
+Reviewed-by: Kees Cook <keescook@chromium.org>
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Will Deacon <will@kernel.org>
+[nd: backport adjusted due to missing:
+ commit addfc38672c7 ("arm64: atomics: avoid out-of-line ll/sc atomics")]
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/include/asm/atomic_lse.h | 76 +++++++++++++++++++++++++++---------
+ arch/arm64/include/asm/lse.h | 6 +-
+ 2 files changed, 60 insertions(+), 22 deletions(-)
+
+--- a/arch/arm64/include/asm/atomic_lse.h
++++ b/arch/arm64/include/asm/atomic_lse.h
+@@ -32,7 +32,9 @@ static inline void atomic_##op(int i, at
+ register int w0 asm ("w0") = i; \
+ register atomic_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(op), \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(op), \
+ " " #asm_op " %w[i], %[v]\n") \
+ : [i] "+r" (w0), [v] "+Q" (v->counter) \
+ : "r" (x1) \
+@@ -52,7 +54,9 @@ static inline int atomic_fetch_##op##nam
+ register int w0 asm ("w0") = i; \
+ register atomic_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC(fetch_##op##name), \
+ /* LSE atomics */ \
+@@ -84,7 +88,9 @@ static inline int atomic_add_return##nam
+ register int w0 asm ("w0") = i; \
+ register atomic_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC(add_return##name) \
+ __nops(1), \
+@@ -110,7 +116,9 @@ static inline void atomic_and(int i, ato
+ register int w0 asm ("w0") = i;
+ register atomic_t *x1 asm ("x1") = v;
+
+- asm volatile(ARM64_LSE_ATOMIC_INSN(
++ asm volatile(
++ __LSE_PREAMBLE
++ ARM64_LSE_ATOMIC_INSN(
+ /* LL/SC */
+ __LL_SC_ATOMIC(and)
+ __nops(1),
+@@ -128,7 +136,9 @@ static inline int atomic_fetch_and##name
+ register int w0 asm ("w0") = i; \
+ register atomic_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC(fetch_and##name) \
+ __nops(1), \
+@@ -154,7 +164,9 @@ static inline void atomic_sub(int i, ato
+ register int w0 asm ("w0") = i;
+ register atomic_t *x1 asm ("x1") = v;
+
+- asm volatile(ARM64_LSE_ATOMIC_INSN(
++ asm volatile(
++ __LSE_PREAMBLE
++ ARM64_LSE_ATOMIC_INSN(
+ /* LL/SC */
+ __LL_SC_ATOMIC(sub)
+ __nops(1),
+@@ -172,7 +184,9 @@ static inline int atomic_sub_return##nam
+ register int w0 asm ("w0") = i; \
+ register atomic_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC(sub_return##name) \
+ __nops(2), \
+@@ -200,7 +214,9 @@ static inline int atomic_fetch_sub##name
+ register int w0 asm ("w0") = i; \
+ register atomic_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC(fetch_sub##name) \
+ __nops(1), \
+@@ -229,7 +245,9 @@ static inline void atomic64_##op(long i,
+ register long x0 asm ("x0") = i; \
+ register atomic64_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(op), \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(op), \
+ " " #asm_op " %[i], %[v]\n") \
+ : [i] "+r" (x0), [v] "+Q" (v->counter) \
+ : "r" (x1) \
+@@ -249,7 +267,9 @@ static inline long atomic64_fetch_##op##
+ register long x0 asm ("x0") = i; \
+ register atomic64_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC64(fetch_##op##name), \
+ /* LSE atomics */ \
+@@ -281,7 +301,9 @@ static inline long atomic64_add_return##
+ register long x0 asm ("x0") = i; \
+ register atomic64_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC64(add_return##name) \
+ __nops(1), \
+@@ -307,7 +329,9 @@ static inline void atomic64_and(long i,
+ register long x0 asm ("x0") = i;
+ register atomic64_t *x1 asm ("x1") = v;
+
+- asm volatile(ARM64_LSE_ATOMIC_INSN(
++ asm volatile(
++ __LSE_PREAMBLE
++ ARM64_LSE_ATOMIC_INSN(
+ /* LL/SC */
+ __LL_SC_ATOMIC64(and)
+ __nops(1),
+@@ -325,7 +349,9 @@ static inline long atomic64_fetch_and##n
+ register long x0 asm ("x0") = i; \
+ register atomic64_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC64(fetch_and##name) \
+ __nops(1), \
+@@ -351,7 +377,9 @@ static inline void atomic64_sub(long i,
+ register long x0 asm ("x0") = i;
+ register atomic64_t *x1 asm ("x1") = v;
+
+- asm volatile(ARM64_LSE_ATOMIC_INSN(
++ asm volatile(
++ __LSE_PREAMBLE
++ ARM64_LSE_ATOMIC_INSN(
+ /* LL/SC */
+ __LL_SC_ATOMIC64(sub)
+ __nops(1),
+@@ -369,7 +397,9 @@ static inline long atomic64_sub_return##
+ register long x0 asm ("x0") = i; \
+ register atomic64_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC64(sub_return##name) \
+ __nops(2), \
+@@ -397,7 +427,9 @@ static inline long atomic64_fetch_sub##n
+ register long x0 asm ("x0") = i; \
+ register atomic64_t *x1 asm ("x1") = v; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_ATOMIC64(fetch_sub##name) \
+ __nops(1), \
+@@ -422,7 +454,9 @@ static inline long atomic64_dec_if_posit
+ {
+ register long x0 asm ("x0") = (long)v;
+
+- asm volatile(ARM64_LSE_ATOMIC_INSN(
++ asm volatile(
++ __LSE_PREAMBLE
++ ARM64_LSE_ATOMIC_INSN(
+ /* LL/SC */
+ __LL_SC_ATOMIC64(dec_if_positive)
+ __nops(6),
+@@ -455,7 +489,9 @@ static inline unsigned long __cmpxchg_ca
+ register unsigned long x1 asm ("x1") = old; \
+ register unsigned long x2 asm ("x2") = new; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_CMPXCHG(name) \
+ __nops(2), \
+@@ -507,7 +543,9 @@ static inline long __cmpxchg_double##nam
+ register unsigned long x3 asm ("x3") = new2; \
+ register unsigned long x4 asm ("x4") = (unsigned long)ptr; \
+ \
+- asm volatile(ARM64_LSE_ATOMIC_INSN( \
++ asm volatile( \
++ __LSE_PREAMBLE \
++ ARM64_LSE_ATOMIC_INSN( \
+ /* LL/SC */ \
+ __LL_SC_CMPXCHG_DBL(name) \
+ __nops(3), \
+--- a/arch/arm64/include/asm/lse.h
++++ b/arch/arm64/include/asm/lse.h
+@@ -4,6 +4,8 @@
+
+ #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
+
++#define __LSE_PREAMBLE ".arch armv8-a+lse\n"
++
+ #include <linux/compiler_types.h>
+ #include <linux/export.h>
+ #include <linux/stringify.h>
+@@ -20,8 +22,6 @@
+
+ #else /* __ASSEMBLER__ */
+
+-__asm__(".arch_extension lse");
+-
+ /* Move the ll/sc atomics out-of-line */
+ #define __LL_SC_INLINE notrace
+ #define __LL_SC_PREFIX(x) __ll_sc_##x
+@@ -33,7 +33,7 @@ __asm__(".arch_extension lse");
+
+ /* In-line patching at runtime */
+ #define ARM64_LSE_ATOMIC_INSN(llsc, lse) \
+- ALTERNATIVE(llsc, lse, ARM64_HAS_LSE_ATOMICS)
++ ALTERNATIVE(llsc, __LSE_PREAMBLE lse, ARM64_HAS_LSE_ATOMICS)
+
+ #endif /* __ASSEMBLER__ */
+ #else /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
--- /dev/null
+From foo@baz Sat Dec 19 01:43:56 PM CET 2020
+From: Vincenzo Frascino <vincenzo.frascino@arm.com>
+Date: Tue, 18 Feb 2020 16:49:06 +0000
+Subject: arm64: lse: Fix LSE atomics with LLVM
+
+From: Vincenzo Frascino <vincenzo.frascino@arm.com>
+
+commit dd1f6308b28edf0452dd5dc7877992903ec61e69 upstream.
+
+Commit e0d5896bd356 ("arm64: lse: fix LSE atomics with LLVM's integrated
+assembler") broke the build when clang is used in connjunction with the
+binutils assembler ("-no-integrated-as"). This happens because
+__LSE_PREAMBLE is defined as ".arch armv8-a+lse", which overrides the
+version of the CPU architecture passed via the "-march" paramter to gas:
+
+$ aarch64-none-linux-gnu-as -EL -I ./arch/arm64/include
+ -I ./arch/arm64/include/generated
+ -I ./include -I ./include
+ -I ./arch/arm64/include/uapi
+ -I ./arch/arm64/include/generated/uapi
+ -I ./include/uapi -I ./include/generated/uapi
+ -I ./init -I ./init
+ -march=armv8.3-a -o init/do_mounts.o
+ /tmp/do_mounts-d7992a.s
+/tmp/do_mounts-d7992a.s: Assembler messages:
+/tmp/do_mounts-d7992a.s:1959: Error: selected processor does not support `autiasp'
+/tmp/do_mounts-d7992a.s:2021: Error: selected processor does not support `paciasp'
+/tmp/do_mounts-d7992a.s:2157: Error: selected processor does not support `autiasp'
+/tmp/do_mounts-d7992a.s:2175: Error: selected processor does not support `paciasp'
+/tmp/do_mounts-d7992a.s:2494: Error: selected processor does not support `autiasp'
+
+Fix the issue by replacing ".arch armv8-a+lse" with ".arch_extension lse".
+Sami confirms that the clang integrated assembler does now support the
+'.arch_extension' directive, so this change will be fine even for LTO
+builds in future.
+
+Fixes: e0d5896bd356cd ("arm64: lse: fix LSE atomics with LLVM's integrated assembler")
+Cc: Catalin Marinas <catalin.marinas@arm.com>
+Cc: Will Deacon <will@kernel.org>
+Reported-by: Amit Kachhap <Amit.Kachhap@arm.com>
+Tested-by: Sami Tolvanen <samitolvanen@google.com>
+Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
+Signed-off-by: Will Deacon <will@kernel.org>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/arm64/include/asm/lse.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/include/asm/lse.h
++++ b/arch/arm64/include/asm/lse.h
+@@ -4,7 +4,7 @@
+
+ #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
+
+-#define __LSE_PREAMBLE ".arch armv8-a+lse\n"
++#define __LSE_PREAMBLE ".arch_extension lse\n"
+
+ #include <linux/compiler_types.h>
+ #include <linux/export.h>
--- /dev/null
+From foo@baz Sat Dec 19 01:41:44 PM CET 2020
+From: Xin Xiong <xiongx18@fudan.edu.cn>
+Date: Sun, 19 Jul 2020 23:45:45 +0800
+Subject: drm: fix drm_dp_mst_port refcount leaks in drm_dp_mst_allocate_vcpi
+
+From: Xin Xiong <xiongx18@fudan.edu.cn>
+
+commit a34a0a632dd991a371fec56431d73279f9c54029 upstream
+
+drm_dp_mst_allocate_vcpi() invokes
+drm_dp_mst_topology_get_port_validated(), which increases the refcount
+of the "port".
+
+These reference counting issues take place in two exception handling
+paths separately. Either when “slots” is less than 0 or when
+drm_dp_init_vcpi() returns a negative value, the function forgets to
+reduce the refcnt increased drm_dp_mst_topology_get_port_validated(),
+which results in a refcount leak.
+
+Fix these issues by pulling up the error handling when "slots" is less
+than 0, and calling drm_dp_mst_topology_put_port() before termination
+when drm_dp_init_vcpi() returns a negative value.
+
+Fixes: 1e797f556c61 ("drm/dp: Split drm_dp_mst_allocate_vcpi")
+Cc: <stable@vger.kernel.org> # v4.12+
+Signed-off-by: Xiyu Yang <xiyuyang19@fudan.edu.cn>
+Signed-off-by: Xin Tan <tanxin.ctf@gmail.com>
+Signed-off-by: Xin Xiong <xiongx18@fudan.edu.cn>
+Reviewed-by: Lyude Paul <lyude@redhat.com>
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20200719154545.GA41231@xin-virtual-machine
+[sudip: use old functions before rename]
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/drm_dp_mst_topology.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/drm_dp_mst_topology.c
++++ b/drivers/gpu/drm/drm_dp_mst_topology.c
+@@ -2706,11 +2706,11 @@ bool drm_dp_mst_allocate_vcpi(struct drm
+ {
+ int ret;
+
+- port = drm_dp_get_validated_port_ref(mgr, port);
+- if (!port)
++ if (slots < 0)
+ return false;
+
+- if (slots < 0)
++ port = drm_dp_get_validated_port_ref(mgr, port);
++ if (!port)
+ return false;
+
+ if (port->vcpi.vcpi > 0) {
+@@ -2725,6 +2725,7 @@ bool drm_dp_mst_allocate_vcpi(struct drm
+ if (ret) {
+ DRM_DEBUG_KMS("failed to init vcpi slots=%d max=63 ret=%d\n",
+ DIV_ROUND_UP(pbn, mgr->pbn_div), ret);
++ drm_dp_put_port(port);
+ goto out;
+ }
+ DRM_DEBUG_KMS("initing vcpi for pbn=%d slots=%d\n",
--- /dev/null
+From foo@baz Sat Dec 19 01:41:13 PM CET 2020
+From: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
+Date: Thu, 13 Aug 2020 09:21:10 +0300
+Subject: drm/xen-front: Fix misused IS_ERR_OR_NULL checks
+
+From: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
+
+commit 14dee058610446aa464254fc5c8e88c7535195e0 upstream
+
+The patch c575b7eeb89f: "drm/xen-front: Add support for Xen PV
+display frontend" from Apr 3, 2018, leads to the following static
+checker warning:
+
+ drivers/gpu/drm/xen/xen_drm_front_gem.c:140 xen_drm_front_gem_create()
+ warn: passing zero to 'ERR_CAST'
+
+drivers/gpu/drm/xen/xen_drm_front_gem.c
+ 133 struct drm_gem_object *xen_drm_front_gem_create(struct drm_device *dev,
+ 134 size_t size)
+ 135 {
+ 136 struct xen_gem_object *xen_obj;
+ 137
+ 138 xen_obj = gem_create(dev, size);
+ 139 if (IS_ERR_OR_NULL(xen_obj))
+ 140 return ERR_CAST(xen_obj);
+
+Fix this and the rest of misused places with IS_ERR_OR_NULL in the
+driver.
+
+Fixes: c575b7eeb89f: "drm/xen-front: Add support for Xen PV display frontend"
+
+Signed-off-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
+Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
+Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com>
+Cc: <stable@vger.kernel.org>
+Link: https://lore.kernel.org/r/20200813062113.11030-3-andr2000@gmail.com
+Signed-off-by: Juergen Gross <jgross@suse.com>
+[sudip: adjust context]
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/xen/xen_drm_front.c | 2 +-
+ drivers/gpu/drm/xen/xen_drm_front_gem.c | 8 ++++----
+ drivers/gpu/drm/xen/xen_drm_front_kms.c | 2 +-
+ 3 files changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/xen/xen_drm_front.c
++++ b/drivers/gpu/drm/xen/xen_drm_front.c
+@@ -410,7 +410,7 @@ static int xen_drm_drv_dumb_create(struc
+ args->size = args->pitch * args->height;
+
+ obj = xen_drm_front_gem_create(dev, args->size);
+- if (IS_ERR_OR_NULL(obj)) {
++ if (IS_ERR(obj)) {
+ ret = PTR_ERR(obj);
+ goto fail;
+ }
+--- a/drivers/gpu/drm/xen/xen_drm_front_gem.c
++++ b/drivers/gpu/drm/xen/xen_drm_front_gem.c
+@@ -85,7 +85,7 @@ static struct xen_gem_object *gem_create
+
+ size = round_up(size, PAGE_SIZE);
+ xen_obj = gem_create_obj(dev, size);
+- if (IS_ERR_OR_NULL(xen_obj))
++ if (IS_ERR(xen_obj))
+ return xen_obj;
+
+ if (drm_info->front_info->cfg.be_alloc) {
+@@ -119,7 +119,7 @@ static struct xen_gem_object *gem_create
+ */
+ xen_obj->num_pages = DIV_ROUND_UP(size, PAGE_SIZE);
+ xen_obj->pages = drm_gem_get_pages(&xen_obj->base);
+- if (IS_ERR_OR_NULL(xen_obj->pages)) {
++ if (IS_ERR(xen_obj->pages)) {
+ ret = PTR_ERR(xen_obj->pages);
+ xen_obj->pages = NULL;
+ goto fail;
+@@ -138,7 +138,7 @@ struct drm_gem_object *xen_drm_front_gem
+ struct xen_gem_object *xen_obj;
+
+ xen_obj = gem_create(dev, size);
+- if (IS_ERR_OR_NULL(xen_obj))
++ if (IS_ERR(xen_obj))
+ return ERR_CAST(xen_obj);
+
+ return &xen_obj->base;
+@@ -196,7 +196,7 @@ xen_drm_front_gem_import_sg_table(struct
+
+ size = attach->dmabuf->size;
+ xen_obj = gem_create_obj(dev, size);
+- if (IS_ERR_OR_NULL(xen_obj))
++ if (IS_ERR(xen_obj))
+ return ERR_CAST(xen_obj);
+
+ ret = gem_alloc_pages_array(xen_obj, size);
+--- a/drivers/gpu/drm/xen/xen_drm_front_kms.c
++++ b/drivers/gpu/drm/xen/xen_drm_front_kms.c
+@@ -59,7 +59,7 @@ fb_create(struct drm_device *dev, struct
+ int ret;
+
+ fb = drm_gem_fb_create_with_funcs(dev, filp, mode_cmd, &fb_funcs);
+- if (IS_ERR_OR_NULL(fb))
++ if (IS_ERR(fb))
+ return fb;
+
+ gem_obj = drm_gem_object_lookup(filp, mode_cmd->handles[0]);
usb-sisusbvga-make-console-support-depend-on-broken.patch
alsa-pcm-oss-fix-potential-out-of-bounds-shift.patch
serial-8250_omap-avoid-fifo-corruption-caused-by-mdr1-access.patch
+drm-xen-front-fix-misused-is_err_or_null-checks.patch
+drm-fix-drm_dp_mst_port-refcount-leaks-in-drm_dp_mst_allocate_vcpi.patch
+arm64-lse-fix-lse-atomics-with-llvm-s-integrated-assembler.patch
+arm64-lse-fix-lse-atomics-with-llvm.patch
+arm64-change-.weak-to-sym_func_start_weak_pi-for-arch-arm64-lib-mem-.s.patch
+x86-resctrl-remove-unused-struct-mbm_state-chunks_bw.patch
+x86-resctrl-fix-incorrect-local-bandwidth-when-mba_sc-is-enabled.patch
--- /dev/null
+From foo@baz Sat Dec 19 01:49:55 PM CET 2020
+From: Xiaochen Shen <xiaochen.shen@intel.com>
+Date: Fri, 4 Dec 2020 14:27:59 +0800
+Subject: x86/resctrl: Fix incorrect local bandwidth when mba_sc is enabled
+
+From: Xiaochen Shen <xiaochen.shen@intel.com>
+
+commit 06c5fe9b12dde1b62821f302f177c972bb1c81f9 upstream
+
+The MBA software controller (mba_sc) is a feedback loop which
+periodically reads MBM counters and tries to restrict the bandwidth
+below a user-specified value. It tags along the MBM counter overflow
+handler to do the updates with 1s interval in mbm_update() and
+update_mba_bw().
+
+The purpose of mbm_update() is to periodically read the MBM counters to
+make sure that the hardware counter doesn't wrap around more than once
+between user samplings. mbm_update() calls __mon_event_count() for local
+bandwidth updating when mba_sc is not enabled, but calls mbm_bw_count()
+instead when mba_sc is enabled. __mon_event_count() will not be called
+for local bandwidth updating in MBM counter overflow handler, but it is
+still called when reading MBM local bandwidth counter file
+'mbm_local_bytes', the call path is as below:
+
+ rdtgroup_mondata_show()
+ mon_event_read()
+ mon_event_count()
+ __mon_event_count()
+
+In __mon_event_count(), m->chunks is updated by delta chunks which is
+calculated from previous MSR value (m->prev_msr) and current MSR value.
+When mba_sc is enabled, m->chunks is also updated in mbm_update() by
+mistake by the delta chunks which is calculated from m->prev_bw_msr
+instead of m->prev_msr. But m->chunks is not used in update_mba_bw() in
+the mba_sc feedback loop.
+
+When reading MBM local bandwidth counter file, m->chunks was changed
+unexpectedly by mbm_bw_count(). As a result, the incorrect local
+bandwidth counter which calculated from incorrect m->chunks is shown to
+the user.
+
+Fix this by removing incorrect m->chunks updating in mbm_bw_count() in
+MBM counter overflow handler, and always calling __mon_event_count() in
+mbm_update() to make sure that the hardware local bandwidth counter
+doesn't wrap around.
+
+Test steps:
+ # Run workload with aggressive memory bandwidth (e.g., 10 GB/s)
+ git clone https://github.com/intel/intel-cmt-cat && cd intel-cmt-cat
+ && make
+ ./tools/membw/membw -c 0 -b 10000 --read
+
+ # Enable MBA software controller
+ mount -t resctrl resctrl -o mba_MBps /sys/fs/resctrl
+
+ # Create control group c1
+ mkdir /sys/fs/resctrl/c1
+
+ # Set MB throttle to 6 GB/s
+ echo "MB:0=6000;1=6000" > /sys/fs/resctrl/c1/schemata
+
+ # Write PID of the workload to tasks file
+ echo `pidof membw` > /sys/fs/resctrl/c1/tasks
+
+ # Read local bytes counters twice with 1s interval, the calculated
+ # local bandwidth is not as expected (approaching to 6 GB/s):
+ local_1=`cat /sys/fs/resctrl/c1/mon_data/mon_L3_00/mbm_local_bytes`
+ sleep 1
+ local_2=`cat /sys/fs/resctrl/c1/mon_data/mon_L3_00/mbm_local_bytes`
+ echo "local b/w (bytes/s):" `expr $local_2 - $local_1`
+
+Before fix:
+ local b/w (bytes/s): 11076796416
+
+After fix:
+ local b/w (bytes/s): 5465014272
+
+Fixes: ba0f26d8529c (x86/intel_rdt/mba_sc: Prepare for feedback loop)
+Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Tony Luck <tony.luck@intel.com>
+Cc: <stable@vger.kernel.org>
+Link: https://lkml.kernel.org/r/1607063279-19437-1-git-send-email-xiaochen.shen@intel.com
+[sudip: manual backport to file at old path]
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/intel_rdt_monitor.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/arch/x86/kernel/cpu/intel_rdt_monitor.c
++++ b/arch/x86/kernel/cpu/intel_rdt_monitor.c
+@@ -290,7 +290,6 @@ static void mbm_bw_count(u32 rmid, struc
+ return;
+
+ chunks = mbm_overflow_count(m->prev_bw_msr, tval);
+- m->chunks += chunks;
+ cur_bw = (chunks * r->mon_scale) >> 20;
+
+ if (m->delta_comp)
+@@ -460,15 +459,14 @@ static void mbm_update(struct rdt_domain
+ }
+ if (is_mbm_local_enabled()) {
+ rr.evtid = QOS_L3_MBM_LOCAL_EVENT_ID;
++ __mon_event_count(rmid, &rr);
+
+ /*
+ * Call the MBA software controller only for the
+ * control groups and when user has enabled
+ * the software controller explicitly.
+ */
+- if (!is_mba_sc(NULL))
+- __mon_event_count(rmid, &rr);
+- else
++ if (is_mba_sc(NULL))
+ mbm_bw_count(rmid, &rr);
+ }
+ }
--- /dev/null
+From foo@baz Sat Dec 19 01:49:42 PM CET 2020
+From: James Morse <james.morse@arm.com>
+Date: Wed, 8 Jul 2020 16:39:20 +0000
+Subject: x86/resctrl: Remove unused struct mbm_state::chunks_bw
+
+From: James Morse <james.morse@arm.com>
+
+commit abe8f12b44250d02937665033a8b750c1bfeb26e upstream
+
+Nothing reads struct mbm_states's chunks_bw value, its a copy of
+chunks. Remove it.
+
+Signed-off-by: James Morse <james.morse@arm.com>
+Signed-off-by: Borislav Petkov <bp@suse.de>
+Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
+Link: https://lkml.kernel.org/r/20200708163929.2783-2-james.morse@arm.com
+[sudip: manual backport to file at old path]
+Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/x86/kernel/cpu/intel_rdt.h | 2 --
+ arch/x86/kernel/cpu/intel_rdt_monitor.c | 3 +--
+ 2 files changed, 1 insertion(+), 4 deletions(-)
+
+--- a/arch/x86/kernel/cpu/intel_rdt.h
++++ b/arch/x86/kernel/cpu/intel_rdt.h
+@@ -251,7 +251,6 @@ struct rftype {
+ * struct mbm_state - status for each MBM counter in each domain
+ * @chunks: Total data moved (multiply by rdt_group.mon_scale to get bytes)
+ * @prev_msr Value of IA32_QM_CTR for this RMID last time we read it
+- * @chunks_bw Total local data moved. Used for bandwidth calculation
+ * @prev_bw_msr:Value of previous IA32_QM_CTR for bandwidth counting
+ * @prev_bw The most recent bandwidth in MBps
+ * @delta_bw Difference between the current and previous bandwidth
+@@ -260,7 +259,6 @@ struct rftype {
+ struct mbm_state {
+ u64 chunks;
+ u64 prev_msr;
+- u64 chunks_bw;
+ u64 prev_bw_msr;
+ u32 prev_bw;
+ u32 delta_bw;
+--- a/arch/x86/kernel/cpu/intel_rdt_monitor.c
++++ b/arch/x86/kernel/cpu/intel_rdt_monitor.c
+@@ -290,8 +290,7 @@ static void mbm_bw_count(u32 rmid, struc
+ return;
+
+ chunks = mbm_overflow_count(m->prev_bw_msr, tval);
+- m->chunks_bw += chunks;
+- m->chunks = m->chunks_bw;
++ m->chunks += chunks;
+ cur_bw = (chunks * r->mon_scale) >> 20;
+
+ if (m->delta_comp)
projects / thirdparty / kernel / stable-queue.git / commitdiff
