--- /dev/null
+From 5208e7ced520a813b4f4774451fbac4e517e78b2 Mon Sep 17 00:00:00 2001
+From: Doug Brown <doug@schmorgal.com>
+Date: Sun, 19 May 2024 12:19:30 -0700
+Subject: serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level
+
+From: Doug Brown <doug@schmorgal.com>
+
+commit 5208e7ced520a813b4f4774451fbac4e517e78b2 upstream.
+
+The FIFO is 64 bytes, but the FCR is configured to fire the TX interrupt
+when the FIFO is half empty (bit 3 = 0). Thus, we should only write 32
+bytes when a TX interrupt occurs.
+
+This fixes a problem observed on the PXA168 that dropped a bunch of TX
+bytes during large transmissions.
+
+Fixes: ab28f51c77cd ("serial: rewrite pxa2xx-uart to use 8250_core")
+Signed-off-by: Doug Brown <doug@schmorgal.com>
+Link: https://lore.kernel.org/r/20240519191929.122202-1-doug@schmorgal.com
+Cc: stable <stable@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/tty/serial/8250/8250_pxa.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/tty/serial/8250/8250_pxa.c
++++ b/drivers/tty/serial/8250/8250_pxa.c
+@@ -124,6 +124,7 @@ static int serial_pxa_probe(struct platf
+ uart.port.regshift = 2;
+ uart.port.irq = irq;
+ uart.port.fifosize = 64;
++ uart.tx_loadsz = 32;
+ uart.port.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE;
+ uart.port.dev = &pdev->dev;
+ uart.port.uartclk = clk_get_rate(data->clk);