zynq: Fix elf header generation

This patch is here because of:
"arm: keep all sections in ELF file"
(sha1: 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7)

Our tools expected to have elf with only LOAD header.
Without this fix also PHDR, INTERP and DYNAMIC headers
are available in ELF.

Problem was introduced by:
Merge tag 'v2014.01' into xilinx/master-next
(sha1: 60513f2031793692e60e3b2fc1930243bb6bb991)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/cpu/armv7/zynq/u-boot.lds
new file mode 100644 (file)
index 0000000..764f04b
--- /dev/null
+++ b/arch/arm/cpu/armv7/zynq/u-boot.lds
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+       . = 0x00000000;
+
+       . = ALIGN(4);
+       .text :
+       {
+               *(.__image_copy_start)
+               CPUDIR/start.o (.text*)
+               *(.text*)
+       }
+
+       . = ALIGN(4);
+       .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+       . = ALIGN(4);
+       .data : {
+               *(.data*)
+       }
+
+       . = ALIGN(4);
+
+       . = .;
+
+       . = ALIGN(4);
+       .u_boot_list : {
+               KEEP(*(SORT(.u_boot_list*)));
+       }
+
+       . = ALIGN(4);
+
+       .image_copy_end :
+       {
+               *(.__image_copy_end)
+       }
+
+       .rel_dyn_start :
+       {
+               *(.__rel_dyn_start)
+       }
+
+       .rel.dyn : {
+               *(.rel*)
+       }
+
+       .rel_dyn_end :
+       {
+               *(.__rel_dyn_end)
+       }
+
+       _end = .;
+
+       /*
+        * Deprecated: this MMU section is used by pxa at present but
+        * should not be used by new boards/CPUs.
+        */
+       . = ALIGN(4096);
+       .mmutable : {
+               *(.mmutable)
+       }
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+       .bss_start __rel_dyn_start (OVERLAY) : {
+               KEEP(*(.__bss_start));
+               __bss_base = .;
+       }
+
+       .bss __bss_base (OVERLAY) : {
+               *(.bss*)
+                . = ALIGN(4);
+                __bss_limit = .;
+       }
+
+       .bss_end __bss_limit (OVERLAY) : {
+               KEEP(*(.__bss_end));
+       }
+
+       /DISCARD/ : { *(.dynsym) }
+       /DISCARD/ : { *(.dynbss*) }
+       /DISCARD/ : { *(.dynstr*) }
+       /DISCARD/ : { *(.dynamic*) }
+       /DISCARD/ : { *(.plt*) }
+       /DISCARD/ : { *(.interp*) }
+       /DISCARD/ : { *(.gnu*) }
+       /DISCARD/ : { *(.ARM.exidx*) }
+       /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+}

diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 94ec88a6f64ac817787dcb1ed3486ac44d684fae..448b152737d7e015c76acce97c3f1cbc8e3951fa 100644 (file)
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -349,6 +349,8 @@
 # define CONFIG_PANIC_HANG
 #endif
 
+#define CONFIG_SYS_LDSCRIPT  "arch/arm/cpu/armv7/zynq/u-boot.lds"
+
 /* SPL part */
 #define CONFIG_SPL
 #define CONFIG_CMD_SPL