arm64: dts: imx8mp-venice-gw74xx: update name of M2SKT_WDIS2# gpio

[ Upstream commit 26a6a9cde64a890997708007d9de25809970eac9 ]

The GW74xx D revision has added a M2SKT_WDIS2# GPIO which routes to the
W_DISABLE2# pin of the M.2 socket. Update the gpio name for consistency.

Fixes: 6a5d95b06d93 ("arm64: dts: imx8mp-venice-gw74xx: add M2SKT_GPIO10 gpio configuration")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
index 568d24265ddf8ea528346252615a1d5064e63a42..12de7cf1e8538e38df2ed6f2c8697d4f7597962a 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -301,7 +301,7 @@
 &gpio3 {
        gpio-line-names =
                "", "", "", "", "", "", "m2_rst", "",
-               "", "", "", "", "", "", "m2_gpio10", "",
+               "", "", "", "", "", "", "m2_wdis2#", "",
                "", "", "", "", "", "", "", "",
                "", "", "", "", "", "", "", "";
 };
@@ -310,7 +310,7 @@
        gpio-line-names =
                "", "", "m2_off#", "", "", "", "", "",
                "", "", "", "", "", "", "", "",
-               "", "", "m2_wdis#", "", "", "", "", "",
+               "", "", "m2_wdis1#", "", "", "", "", "",
                "", "", "", "", "", "", "", "rs485_en";
 };
 
@@ -811,14 +811,14 @@
                        MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09     0x40000040 /* DIO0 */
                        MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11     0x40000040 /* DIO1 */
                        MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02      0x40000040 /* M2SKT_OFF# */
-                       MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18      0x40000150 /* M2SKT_WDIS# */
+                       MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18      0x40000150 /* M2SKT_WDIS1# */
                        MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06      0x40000040 /* M2SKT_PIN20 */
                        MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11     0x40000040 /* M2SKT_PIN22 */
                        MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13        0x40000150 /* PCIE1_WDIS# */
                        MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14        0x40000150 /* PCIE3_WDIS# */
                        MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18      0x40000150 /* PCIE2_WDIS# */
                        MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06    0x40000040 /* M2SKT_RST# */
-                       MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14       0x40000040 /* M2SKT_GPIO10 */
+                       MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14       0x40000150 /* M2KST_WDIS2# */
                        MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01       0x40000104 /* UART_TERM */
                        MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31      0x40000104 /* UART_RS485 */
                        MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00       0x40000104 /* UART_HALF */