drm/amd/pm/si: Hook up VCE1 to SI DPM

On SI GPUs, the SMC needs to be aware of whether or not the VCE1
is used. The VCE1 is enabled/disabled through the DPM code.

Also print VCE clocks in amdgpu_pm_info.
Users can inspect the current power state using:
cat /sys/kernel/debug/dri/<card>/amdgpu_pm_info

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
index 020e05c137e4343b5771fb7483aa60dc617f2749..1f539cc65f41ffd65d9713c38d1670da79f80f23 100644 (file)
--- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
+++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
@@ -7046,13 +7046,20 @@ static void si_set_vce_clock(struct amdgpu_device *adev,
        if ((old_rps->evclk != new_rps->evclk) ||
            (old_rps->ecclk != new_rps->ecclk)) {
                /* Turn the clocks on when encoding, off otherwise */
+               dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk);
+
                if (new_rps->evclk || new_rps->ecclk) {
-                       /* Place holder for future VCE1.0 porting to amdgpu
-                       vce_v1_0_enable_mgcg(adev, false, false);*/
+                       amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);
+                       amdgpu_device_ip_set_clockgating_state(
+                               adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE);
+                       amdgpu_device_ip_set_powergating_state(
+                               adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_UNGATE);
                } else {
-                       /* Place holder for future VCE1.0 porting to amdgpu
-                       vce_v1_0_enable_mgcg(adev, true, false);
-                       amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/
+                       amdgpu_device_ip_set_powergating_state(
+                               adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE);
+                       amdgpu_device_ip_set_clockgating_state(
+                               adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE);
+                       amdgpu_asic_set_vce_clocks(adev, 0, 0);
                }
        }
 }
@@ -7574,6 +7581,7 @@ static void si_dpm_debugfs_print_current_performance_level(void *handle,
        } else {
                pl = &ps->performance_levels[current_index];
                seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
+               seq_printf(m, "vce    evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk);
                seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
                           current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
        }