Cache simulation requires strict INCEIP updating so that the boundaries between

individual x86 instructions can be found when instrumenting UCode.  However,
EIP is not needed during execution, because the x86 instr addresses are copied
into the cost-centres.  So now they INCEIPs are removed during the
instrumentation step once their task is done.

This reduces running times by about 3--7%, and translation sizes by about 9%
(code expansion reduced from about 11x to about 10x).

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@550

diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index 05f4186f7b45eb744a5ed9b01842e144961759d3..6cfc2a5d3e40205b5895663a846500c6098d15cb 100644 (file)
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -654,7 +654,14 @@ UCodeBlock* VG_(cachesim_instrument)(UCodeBlock* cb_in, Addr orig_addr)
                uLiteral(cb, VGOFF_(cachesim_log_mem_instr));
             }
 
-            VG_(copyUInstr)(cb, u_in);
+            /* Strict INCEIP updating is required so each x86 instruction's
+             * UCode is clearly marked.  But once we're here, we've found the
+             * end of the x86 instruction and the INCEIP isn't needed any
+             * more -- EIP is never referenced during operation, because the
+             * x86 instr addresses have been squirreled away in the CC.  So
+             * chop it out to save time and space. */
+            if (INCEIP != u_in->opcode)
+               VG_(copyUInstr)(cb, u_in);
 
             /* Update BBCC_ptr, EIP, de-init read/write temps for next instr */
             BBCC_ptr   += CC_size; 

diff --git a/vg_cachesim.c b/vg_cachesim.c
index 05f4186f7b45eb744a5ed9b01842e144961759d3..6cfc2a5d3e40205b5895663a846500c6098d15cb 100644 (file)
--- a/vg_cachesim.c
+++ b/vg_cachesim.c
@@ -654,7 +654,14 @@ UCodeBlock* VG_(cachesim_instrument)(UCodeBlock* cb_in, Addr orig_addr)
                uLiteral(cb, VGOFF_(cachesim_log_mem_instr));
             }
 
-            VG_(copyUInstr)(cb, u_in);
+            /* Strict INCEIP updating is required so each x86 instruction's
+             * UCode is clearly marked.  But once we're here, we've found the
+             * end of the x86 instruction and the INCEIP isn't needed any
+             * more -- EIP is never referenced during operation, because the
+             * x86 instr addresses have been squirreled away in the CC.  So
+             * chop it out to save time and space. */
+            if (INCEIP != u_in->opcode)
+               VG_(copyUInstr)(cb, u_in);
 
             /* Update BBCC_ptr, EIP, de-init read/write temps for next instr */
             BBCC_ptr   += CC_size;