Merge tag 'kvmarm-fixes-7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmar...

KVM/arm64 fixes for 7.0, take #1

- Make sure we don't leak any S1POE state from guest to guest when
  the feature is supported on the HW, but not enabled on the host

- Propagate the ID registers from the host into non-protected VMs
  managed by pKVM, ensuring that the guest sees the intended feature set

- Drop double kern_hyp_va() from unpin_host_sve_state(), which could
  bite us if we were to change kern_hyp_va() to not being idempotent

- Don't leak stage-2 mappings in protected mode

- Correctly align the faulting address when dealing with single page
  stage-2 mappings for PAGE_SIZE > 4kB

- Fix detection of virtualisation-capable GICv5 IRS, due to the
  maintainer being obviously fat fingered...

- Remove duplication of code retrieving the ASID for the purpose of
  S1 PT handling

- Fix slightly abusive const-ification in vgic_set_kvm_info()

diff --cc arch/arm64/kvm/mmu.c
Simple merge

diff --cc arch/arm64/kvm/nested.c
Simple merge

diff --cc drivers/irqchip/irq-gic-v5-irs.c
index e518e5dfede78379788c47e8fd56d1de3c43a39b,4ed2bfa17c015eddf5a6392d9e9a8981a7e4e7c4..f3fce0b1e25d96eee651f03b8423c4c9317d4f5b
--- 1/drivers/irqchip/irq-gic-v5-irs.c
--- 2/drivers/irqchip/irq-gic-v5-irs.c
+++ b/drivers/irqchip/irq-gic-v5-irs.c
@@@ -677,49 -678,7 +677,49 @@@ static void irs_setup_pri_bits(u32 idr1
        }
  }
  
 -static int __init gicv5_irs_init(struct device_node *node)
 +static int __init gicv5_irs_init(struct gicv5_irs_chip_data *irs_data)
 +{
 +      u32 spi_count, idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR2);
 +
 +      if (WARN(!FIELD_GET(GICV5_IRS_IDR2_LPI, idr),
 +               "LPI support not available - no IPIs, can't proceed\n")) {
 +              return -ENODEV;
 +      }
 +
 +      idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR7);
 +      irs_data->spi_min = FIELD_GET(GICV5_IRS_IDR7_SPI_BASE, idr);
 +
 +      idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR6);
 +      irs_data->spi_range = FIELD_GET(GICV5_IRS_IDR6_SPI_IRS_RANGE, idr);
 +
 +      /*
 +       * Do the global setting only on the first IRS.
 +       * Global properties (iaffid_bits, global spi count) are guaranteed to
 +       * be consistent across IRSes by the architecture.
 +       */
 +      if (list_empty(&irs_nodes)) {
 +              idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR0);
-               gicv5_global_data.virt_capable = !FIELD_GET(GICV5_IRS_IDR0_VIRT, idr);
++              gicv5_global_data.virt_capable = !!FIELD_GET(GICV5_IRS_IDR0_VIRT, idr);
 +
 +              idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1);
 +              irs_setup_pri_bits(idr);
 +
 +              idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR5);
 +
 +              spi_count = FIELD_GET(GICV5_IRS_IDR5_SPI_RANGE, idr);
 +              gicv5_global_data.global_spi_count = spi_count;
 +
 +              gicv5_init_lpi_domain();
 +
 +              pr_debug("Detected %u SPIs globally\n", spi_count);
 +      }
 +
 +      list_add_tail(&irs_data->entry, &irs_nodes);
 +
 +      return 0;
 +}
 +
 +static int __init gicv5_irs_of_init(struct device_node *node)
  {
        struct gicv5_irs_chip_data *irs_data;
        void __iomem *irs_base;