wifi: ath12k: Flush the posted write after writing to PCIE_SOC_GLOBAL_RESET

ath12k_pci_soc_global_reset() tries to reset the device by writing to the
PCIE_SOC_GLOBAL_RESET register. But it doesn't do a read-back to ensure
that the write gets flushed to the device before the delay.

This may lead to the delay on the host to be insufficient, if the posted
write doesn't reach the device before the delay.

So add a read-back after writing to the PCIE_SOC_GLOBAL_RESET register and
before the delay.

Compile tested only.
Tested-on: QCN9274 hw2.0 PCI WLAN.WBE.1.6-01243-QCAHKSWPL_SILICONZ-1

Fixes: d889913205cf ("wifi: ath12k: driver for Qualcomm Wi-Fi 7 devices")
Reported-by: Alex Williamson <alex@shazbot.org>
Closes: https://lore.kernel.org/linux-pci/20260622160822.09350246@shazbot.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Baochen Qiang <baochen.qiang@oss.qualcomm.com>
Reviewed-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
Tested-by: Raj Kumar Bhagat <raj.bhagat@oss.qualcomm.com>
Link: https://patch.msgid.link/20260623141649.41087-2-manivannan.sadhasivam@oss.qualcomm.com
Signed-off-by: Jeff Johnson <jeff.johnson@oss.qualcomm.com>

diff --git a/drivers/net/wireless/ath/ath12k/pci.c b/drivers/net/wireless/ath/ath12k/pci.c
index d9a22d6afbb020059d7e3163198375fde89de1eb..fee4129ea4055b4d84f4a9d812627a736669a045 100644 (file)
--- a/drivers/net/wireless/ath/ath12k/pci.c
+++ b/drivers/net/wireless/ath/ath12k/pci.c
@@ -188,6 +188,8 @@ static void ath12k_pci_soc_global_reset(struct ath12k_base *ab)
        val |= PCIE_SOC_GLOBAL_RESET_V;
 
        ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
+       /* Flush the posted write to the device */
+       ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
 
        /* TODO: exact time to sleep is uncertain */
        delay = 10;
@@ -197,6 +199,8 @@ static void ath12k_pci_soc_global_reset(struct ath12k_base *ab)
        val &= ~PCIE_SOC_GLOBAL_RESET_V;
 
        ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
+       /* Flush the posted write to the device */
+       ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
 
        mdelay(delay);