riscv: dts: thead: add DPU and HDMI device tree nodes

T-Head TH1520 SoC contains a Verisilicon DC8200 display controller
(called DPU in manual) and a Synopsys DesignWare HDMI TX controller.

Add device tree nodes to them.

Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Tested-by: Han Gao <gaohan@iscas.ac.cn>
Tested-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <fustini@kernel.org>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Drew Fustini <fustini@kernel.org>

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index bd5d33840884e440ffc1c35c400d8a2642c1cfb2..b663077428940fee49216017f87c4594038d2357 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -585,6 +585,72 @@
                        #clock-cells = <1>;
                };
 
+               hdmi: hdmi@ffef540000 {
+                       compatible = "thead,th1520-dw-hdmi";
+                       reg = <0xff 0xef540000 0x0 0x40000>;
+                       reg-io-width = <4>;
+                       interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk_vo CLK_HDMI_PCLK>,
+                                <&clk_vo CLK_HDMI_SFR>,
+                                <&clk_vo CLK_HDMI_CEC>,
+                                <&clk_vo CLK_HDMI_PIXCLK>;
+                       clock-names = "iahb", "isfr", "cec", "pix";
+                       resets = <&rst TH1520_RESET_ID_HDMI>,
+                                <&rst TH1520_RESET_ID_HDMI_APB>;
+                       reset-names = "main", "apb";
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+
+                                       hdmi_in: endpoint {
+                                               remote-endpoint = <&dpu_out_dp1>;
+                                       };
+                               };
+
+                               hdmi_out_port: port@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
+               dpu: display@ffef600000 {
+                       compatible = "thead,th1520-dc8200", "verisilicon,dc";
+                       reg = <0xff 0xef600000 0x0 0x100000>;
+                       interrupts = <93 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk_vo CLK_DPU_CCLK>,
+                                <&clk_vo CLK_DPU_ACLK>,
+                                <&clk_vo CLK_DPU_HCLK>,
+                                <&clk_vo CLK_DPU_PIXELCLK0>,
+                                <&clk_vo CLK_DPU_PIXELCLK1>;
+                       clock-names = "core", "axi", "ahb", "pix0", "pix1";
+                       resets = <&rst TH1520_RESET_ID_DPU_CORE>,
+                                <&rst TH1520_RESET_ID_DPU_AXI>,
+                                <&rst TH1520_RESET_ID_DPU_AHB>;
+                       reset-names = "core", "axi", "ahb";
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               dpu_port1: port@1 {
+                                       reg = <1>;
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       dpu_out_dp1: endpoint@1 {
+                                               reg = <1>;
+                                               remote-endpoint = <&hdmi_in>;
+                                       };
+                               };
+                       };
+               };
+
                dmac0: dma-controller@ffefc00000 {
                        compatible = "snps,axi-dma-1.01a";
                        reg = <0xff 0xefc00000 0x0 0x1000>;