drm/xe: Implement recent spec updates to Wa_16025250150

The hardware teams noticed that the originally documented workaround
steps for Wa_16025250150 may not be sufficient to fully avoid a hardware
issue.  The workaround documentation has been augmented to suggest
programming one additional register; make the corresponding change in
the driver.

Fixes: 7654d51f1fd8 ("drm/xe/xe2hpg: Add Wa_16025250150")
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patch.msgid.link/20260319-wa_16025250150_part2-v1-1-46b1de1a31b2@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
(cherry picked from commit a31566762d4075646a8a2214586158b681e94305)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 24fc64fc832e983e8c558af20d3396f853bacb7b..9d66f168ab8a7a244b493db7b8675a43f10fd61d 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -553,6 +553,7 @@
 #define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32)
 #define   FORCE_SLM_FENCE_SCOPE_TO_TILE                REG_BIT(42 - 32)
 #define   FORCE_UGM_FENCE_SCOPE_TO_TILE                REG_BIT(41 - 32)
+#define   L3_128B_256B_WRT_DIS                 REG_BIT(40 - 32)
 #define   MAXREQS_PER_BANK                     REG_GENMASK(39 - 32, 37 - 32)
 #define   DISABLE_128B_EVICTION_COMMAND_UDW    REG_BIT(36 - 32)
 

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 462c2fa712e01dd932a775c3b663824886cb090a..d7e309ad9abaf5d332d858d24c8d3cc8b4a67913 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -247,7 +247,8 @@ static const struct xe_rtp_entry_sr gt_was[] = {
                                   LSN_DIM_Z_WGT_MASK,
                                   LSN_LNI_WGT(1) | LSN_LNE_WGT(1) |
                                   LSN_DIM_X_WGT(1) | LSN_DIM_Y_WGT(1) |
-                                  LSN_DIM_Z_WGT(1)))
+                                  LSN_DIM_Z_WGT(1)),
+                       SET(LSC_CHICKEN_BIT_0_UDW, L3_128B_256B_WRT_DIS))
        },
 
        /* Xe2_HPM */