--- /dev/null
+From a9a1ac44074ff8cab7d519277f93341e14557f83 Mon Sep 17 00:00:00 2001
+From: Martin Leung <Martin.Leung@amd.com>
+Date: Fri, 15 Oct 2021 17:36:51 -0400
+Subject: drm/amd/display: Manually adjust strobe for DCN303
+
+From: Martin Leung <Martin.Leung@amd.com>
+
+commit a9a1ac44074ff8cab7d519277f93341e14557f83 upstream.
+
+why:
+DCN303's 4 channel SOC BB causes problems at strobe
+
+how:
+workaround to manually adjust strobe calculation using FCLK
+restrict.
+
+Reviewed-by: Jun Lei <Jun.Lei@amd.com>
+Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
+Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
+Signed-off-by: Martin Leung <Martin.Leung@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
+@@ -1344,6 +1344,20 @@ void dcn303_update_bw_bounding_box(struc
+ dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
+ dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
+ }
++
++ // WA: patch strobe modes to compensate for DCN303 BW issue
++ if (dcn3_03_soc.num_chans <= 4) {
++ for (i = 0; i < dcn3_03_soc.num_states; i++) {
++ if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700)
++ break;
++
++ if (dcn3_03_soc.clock_limits[i].dram_speed_mts >= 1500) {
++ dcn3_03_soc.clock_limits[i].dcfclk_mhz = 100;
++ dcn3_03_soc.clock_limits[i].fabricclk_mhz = 100;
++ }
++ }
++ }
++
+ /* re-init DML with updated bb */
+ dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
+ if (dc->current_state)