--- /dev/null
+From 1c6725897788e5e78c35af3b16b910dfedd79b8d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 11 Sep 2018 04:31:49 +0100
+Subject: ARM: 8788/1: ftrace: remove old mcount support
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit d3c61619568c88d48eccd5e74b4f84faa1440652 upstream.
+
+Commit cafa0010cd51 ("Raise the minimum required gcc version to 4.6")
+raised the minimum GCC version to 4.6. Old mcount is only required for
+GCC versions older than 4.4.0. Hence old mcount support can be dropped
+too.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/Kconfig.debug | 5 ---
+ arch/arm/include/asm/ftrace.h | 3 --
+ arch/arm/kernel/armksyms.c | 3 --
+ arch/arm/kernel/entry-ftrace.S | 75 ++--------------------------------
+ arch/arm/kernel/ftrace.c | 51 -----------------------
+ 5 files changed, 4 insertions(+), 133 deletions(-)
+
+diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
+index bee0ba1d1cfb..631ad56fd9a8 100644
+--- a/arch/arm/Kconfig.debug
++++ b/arch/arm/Kconfig.debug
+@@ -70,11 +70,6 @@ config ARM_UNWIND
+ the performance is not affected. Currently, this feature
+ only works with EABI compilers. If unsure say Y.
+
+-config OLD_MCOUNT
+- bool
+- depends on FUNCTION_TRACER && FRAME_POINTER
+- default y
+-
+ config DEBUG_USER
+ bool "Verbose user fault messages"
+ help
+diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
+index 9e842ff41768..18b0197f2384 100644
+--- a/arch/arm/include/asm/ftrace.h
++++ b/arch/arm/include/asm/ftrace.h
+@@ -16,9 +16,6 @@ extern void __gnu_mcount_nc(void);
+
+ #ifdef CONFIG_DYNAMIC_FTRACE
+ struct dyn_arch_ftrace {
+-#ifdef CONFIG_OLD_MCOUNT
+- bool old_mcount;
+-#endif
+ };
+
+ static inline unsigned long ftrace_call_adjust(unsigned long addr)
+diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
+index 783fbb4de5f9..8fa2dc21d332 100644
+--- a/arch/arm/kernel/armksyms.c
++++ b/arch/arm/kernel/armksyms.c
+@@ -167,9 +167,6 @@ EXPORT_SYMBOL(_find_next_bit_be);
+ #endif
+
+ #ifdef CONFIG_FUNCTION_TRACER
+-#ifdef CONFIG_OLD_MCOUNT
+-EXPORT_SYMBOL(mcount);
+-#endif
+ EXPORT_SYMBOL(__gnu_mcount_nc);
+ #endif
+
+diff --git a/arch/arm/kernel/entry-ftrace.S b/arch/arm/kernel/entry-ftrace.S
+index efcd9f25a14b..0be69e551a64 100644
+--- a/arch/arm/kernel/entry-ftrace.S
++++ b/arch/arm/kernel/entry-ftrace.S
+@@ -15,23 +15,8 @@
+ * start of every function. In mcount, apart from the function's address (in
+ * lr), we need to get hold of the function's caller's address.
+ *
+- * Older GCCs (pre-4.4) inserted a call to a routine called mcount like this:
+- *
+- * bl mcount
+- *
+- * These versions have the limitation that in order for the mcount routine to
+- * be able to determine the function's caller's address, an APCS-style frame
+- * pointer (which is set up with something like the code below) is required.
+- *
+- * mov ip, sp
+- * push {fp, ip, lr, pc}
+- * sub fp, ip, #4
+- *
+- * With EABI, these frame pointers are not available unless -mapcs-frame is
+- * specified, and if building as Thumb-2, not even then.
+- *
+- * Newer GCCs (4.4+) solve this problem by introducing a new version of mcount,
+- * with call sites like:
++ * Newer GCCs (4.4+) solve this problem by using a version of mcount with call
++ * sites like:
+ *
+ * push {lr}
+ * bl __gnu_mcount_nc
+@@ -46,17 +31,10 @@
+ * allows it to be clobbered in subroutines and doesn't use it to hold
+ * parameters.)
+ *
+- * When using dynamic ftrace, we patch out the mcount call by a "mov r0, r0"
+- * for the mcount case, and a "pop {lr}" for the __gnu_mcount_nc case (see
+- * arch/arm/kernel/ftrace.c).
++ * When using dynamic ftrace, we patch out the mcount call by a "pop {lr}"
++ * instead of the __gnu_mcount_nc call (see arch/arm/kernel/ftrace.c).
+ */
+
+-#ifndef CONFIG_OLD_MCOUNT
+-#if (__GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))
+-#error Ftrace requires CONFIG_FRAME_POINTER=y with GCC older than 4.4.0.
+-#endif
+-#endif
+-
+ .macro mcount_adjust_addr rd, rn
+ bic \rd, \rn, #1 @ clear the Thumb bit if present
+ sub \rd, \rd, #MCOUNT_INSN_SIZE
+@@ -209,51 +187,6 @@ ftrace_graph_call\suffix:
+ mcount_exit
+ .endm
+
+-#ifdef CONFIG_OLD_MCOUNT
+-/*
+- * mcount
+- */
+-
+-.macro mcount_enter
+- stmdb sp!, {r0-r3, lr}
+-.endm
+-
+-.macro mcount_get_lr reg
+- ldr \reg, [fp, #-4]
+-.endm
+-
+-.macro mcount_exit
+- ldr lr, [fp, #-4]
+- ldmia sp!, {r0-r3, pc}
+-.endm
+-
+-ENTRY(mcount)
+-#ifdef CONFIG_DYNAMIC_FTRACE
+- stmdb sp!, {lr}
+- ldr lr, [fp, #-4]
+- ldmia sp!, {pc}
+-#else
+- __mcount _old
+-#endif
+-ENDPROC(mcount)
+-
+-#ifdef CONFIG_DYNAMIC_FTRACE
+-ENTRY(ftrace_caller_old)
+- __ftrace_caller _old
+-ENDPROC(ftrace_caller_old)
+-#endif
+-
+-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+-ENTRY(ftrace_graph_caller_old)
+- __ftrace_graph_caller
+-ENDPROC(ftrace_graph_caller_old)
+-#endif
+-
+-.purgem mcount_enter
+-.purgem mcount_get_lr
+-.purgem mcount_exit
+-#endif
+-
+ /*
+ * __gnu_mcount_nc
+ */
+diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
+index ee673c09aa6c..bda949fd84e8 100644
+--- a/arch/arm/kernel/ftrace.c
++++ b/arch/arm/kernel/ftrace.c
+@@ -47,30 +47,6 @@ void arch_ftrace_update_code(int command)
+ stop_machine(__ftrace_modify_code, &command, NULL);
+ }
+
+-#ifdef CONFIG_OLD_MCOUNT
+-#define OLD_MCOUNT_ADDR ((unsigned long) mcount)
+-#define OLD_FTRACE_ADDR ((unsigned long) ftrace_caller_old)
+-
+-#define OLD_NOP 0xe1a00000 /* mov r0, r0 */
+-
+-static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec)
+-{
+- return rec->arch.old_mcount ? OLD_NOP : NOP;
+-}
+-
+-static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
+-{
+- if (!rec->arch.old_mcount)
+- return addr;
+-
+- if (addr == MCOUNT_ADDR)
+- addr = OLD_MCOUNT_ADDR;
+- else if (addr == FTRACE_ADDR)
+- addr = OLD_FTRACE_ADDR;
+-
+- return addr;
+-}
+-#else
+ static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec)
+ {
+ return NOP;
+@@ -80,7 +56,6 @@ static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
+ {
+ return addr;
+ }
+-#endif
+
+ int ftrace_arch_code_modify_prepare(void)
+ {
+@@ -150,15 +125,6 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
+ }
+ #endif
+
+-#ifdef CONFIG_OLD_MCOUNT
+- if (!ret) {
+- pc = (unsigned long)&ftrace_call_old;
+- new = ftrace_call_replace(pc, (unsigned long)func);
+-
+- ret = ftrace_modify_code(pc, 0, new, false);
+- }
+-#endif
+-
+ return ret;
+ }
+
+@@ -203,16 +169,6 @@ int ftrace_make_nop(struct module *mod,
+ new = ftrace_nop_replace(rec);
+ ret = ftrace_modify_code(ip, old, new, true);
+
+-#ifdef CONFIG_OLD_MCOUNT
+- if (ret == -EINVAL && addr == MCOUNT_ADDR) {
+- rec->arch.old_mcount = true;
+-
+- old = ftrace_call_replace(ip, adjust_address(rec, addr));
+- new = ftrace_nop_replace(rec);
+- ret = ftrace_modify_code(ip, old, new, true);
+- }
+-#endif
+-
+ return ret;
+ }
+
+@@ -275,13 +231,6 @@ static int ftrace_modify_graph_caller(bool enable)
+ #endif
+
+
+-#ifdef CONFIG_OLD_MCOUNT
+- if (!ret)
+- ret = __ftrace_modify_caller(&ftrace_graph_call_old,
+- ftrace_graph_caller_old,
+- enable);
+-#endif
+-
+ return ret;
+ }
+
+--
+2.30.1
+
--- /dev/null
+From e6de881ccc42a80f5854bb3cea47682b4a62d6ed Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 30 Sep 2018 23:02:33 +0100
+Subject: ARM: 8800/1: use choice for kernel unwinders
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit f9b58e8c7d031b0daa5c9a9ee27f5a4028ba53ac upstream.
+
+While in theory multiple unwinders could be compiled in, it does
+not make sense in practise. Use a choice to make the unwinder
+selection mutually exclusive and mandatory.
+
+Already before this commit it has not been possible to deselect
+FRAME_POINTER. Remove the obsolete comment.
+
+Furthermore, to produce a meaningful backtrace with FRAME_POINTER
+enabled the kernel needs a specific function prologue:
+ mov ip, sp
+ stmfd sp!, {fp, ip, lr, pc}
+ sub fp, ip, #4
+
+To get to the required prologue gcc uses apcs and no-sched-prolog.
+This compiler options are not available on clang, and clang is not
+able to generate the required prologue. Make the FRAME_POINTER
+config symbol depending on !clang.
+
+Suggested-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Reviewed-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/Kconfig.debug | 44 +++++++++++++++++++++++++++---------------
+ lib/Kconfig.debug | 6 +++---
+ 2 files changed, 31 insertions(+), 19 deletions(-)
+
+diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
+index 631ad56fd9a8..9d363399cb35 100644
+--- a/arch/arm/Kconfig.debug
++++ b/arch/arm/Kconfig.debug
+@@ -45,30 +45,42 @@ config DEBUG_WX
+
+ If in doubt, say "Y".
+
+-# RMK wants arm kernels compiled with frame pointers or stack unwinding.
+-# If you know what you are doing and are willing to live without stack
+-# traces, you can get a slightly smaller kernel by setting this option to
+-# n, but then RMK will have to kill you ;).
+-config FRAME_POINTER
+- bool
+- depends on !THUMB2_KERNEL
+- default y if !ARM_UNWIND || FUNCTION_GRAPH_TRACER
++choice
++ prompt "Choose kernel unwinder"
++ default UNWINDER_ARM if AEABI && !FUNCTION_GRAPH_TRACER
++ default UNWINDER_FRAME_POINTER if !AEABI || FUNCTION_GRAPH_TRACER
++ help
++ This determines which method will be used for unwinding kernel stack
++ traces for panics, oopses, bugs, warnings, perf, /proc/<pid>/stack,
++ livepatch, lockdep, and more.
++
++config UNWINDER_FRAME_POINTER
++ bool "Frame pointer unwinder"
++ depends on !THUMB2_KERNEL && !CC_IS_CLANG
++ select ARCH_WANT_FRAME_POINTERS
++ select FRAME_POINTER
+ help
+- If you say N here, the resulting kernel will be slightly smaller and
+- faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled,
+- when a problem occurs with the kernel, the information that is
+- reported is severely limited.
++ This option enables the frame pointer unwinder for unwinding
++ kernel stack traces.
+
+-config ARM_UNWIND
+- bool "Enable stack unwinding support (EXPERIMENTAL)"
++config UNWINDER_ARM
++ bool "ARM EABI stack unwinder"
+ depends on AEABI
+- default y
++ select ARM_UNWIND
+ help
+ This option enables stack unwinding support in the kernel
+ using the information automatically generated by the
+ compiler. The resulting kernel image is slightly bigger but
+ the performance is not affected. Currently, this feature
+- only works with EABI compilers. If unsure say Y.
++ only works with EABI compilers.
++
++endchoice
++
++config ARM_UNWIND
++ bool
++
++config FRAME_POINTER
++ bool
+
+ config DEBUG_USER
+ bool "Verbose user fault messages"
+diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
+index 46a910acce3f..8a23abc4b326 100644
+--- a/lib/Kconfig.debug
++++ b/lib/Kconfig.debug
+@@ -1179,7 +1179,7 @@ config LOCKDEP
+ bool
+ depends on DEBUG_KERNEL && LOCK_DEBUGGING_SUPPORT
+ select STACKTRACE
+- select FRAME_POINTER if !MIPS && !PPC && !ARM_UNWIND && !S390 && !MICROBLAZE && !ARC && !X86
++ select FRAME_POINTER if !MIPS && !PPC && !ARM && !S390 && !MICROBLAZE && !ARC && !X86
+ select KALLSYMS
+ select KALLSYMS_ALL
+
+@@ -1590,7 +1590,7 @@ config FAULT_INJECTION_STACKTRACE_FILTER
+ depends on FAULT_INJECTION_DEBUG_FS && STACKTRACE_SUPPORT
+ depends on !X86_64
+ select STACKTRACE
+- select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND && !ARC && !X86
++ select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM && !ARC && !X86
+ help
+ Provide stacktrace filter for fault-injection capabilities
+
+@@ -1599,7 +1599,7 @@ config LATENCYTOP
+ depends on DEBUG_KERNEL
+ depends on STACKTRACE_SUPPORT
+ depends on PROC_FS
+- select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM_UNWIND && !ARC && !X86
++ select FRAME_POINTER if !MIPS && !PPC && !S390 && !MICROBLAZE && !ARM && !ARC && !X86
+ select KALLSYMS
+ select KALLSYMS_ALL
+ select STACKTRACE
+--
+2.30.1
+
--- /dev/null
+From 929b17b160b52fc144d8c51a716747f90830f307 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 24 Jan 2019 21:41:59 +0100
+Subject: ARM: 8827/1: fix argument count to match macro definition
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit baf2df8e15be22b8bd24bdd6fd4575b6641bcfd1 upstream.
+
+The macro str8w takes 10 arguments, abort being the 10th. In this
+particular instantiation the abort argument is passed as 11th
+argument leading to an error when using LLVM's integrated
+assembler:
+ <instantiation>:46:47: error: too many positional arguments
+ str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
+ ^
+ arch/arm/lib/copy_template.S:277:5: note: while in macro instantiation
+ 18: forward_copy_shift pull=24 push=8
+ ^
+
+The argument is not used in the macro hence this does not change
+code generation.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Reviewed-by: Nicolas Pitre <nico@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/lib/copy_template.S | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
+index 652e4d98cd47..2d54491b0e22 100644
+--- a/arch/arm/lib/copy_template.S
++++ b/arch/arm/lib/copy_template.S
+@@ -241,7 +241,7 @@
+ orr r9, r9, ip, lspush #\push
+ mov ip, ip, lspull #\pull
+ orr ip, ip, lr, lspush #\push
+- str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
++ str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, abort=19f
+ bge 12b
+ PLD( cmn r2, #96 )
+ PLD( bge 13b )
+--
+2.30.1
+
--- /dev/null
+From 256b86b38ac554ba3b5c2723fd1d2271971d3a7b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 24 Jan 2019 21:42:54 +0100
+Subject: ARM: 8828/1: uaccess: use unified assembler language syntax
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit 32fdb046ac43aa884d960165072ca37b26d78543 upstream.
+
+Convert the conditional infix to a postfix to make sure this inline
+assembly is unified syntax. Since gcc assumes non-unified syntax
+when emitting ARM instructions, make sure to define the syntax as
+unified.
+
+This allows to use LLVM's integrated assembler.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/include/asm/uaccess.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
+index 6390a40f16e7..a50f9b4e2574 100644
+--- a/arch/arm/include/asm/uaccess.h
++++ b/arch/arm/include/asm/uaccess.h
+@@ -86,7 +86,8 @@ static inline void set_fs(mm_segment_t fs)
+ #define __range_ok(addr, size) ({ \
+ unsigned long flag, roksum; \
+ __chk_user_ptr(addr); \
+- __asm__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \
++ __asm__(".syntax unified\n" \
++ "adds %1, %2, %3; sbcscc %1, %1, %0; movcc %0, #0" \
+ : "=&r" (flag), "=&r" (roksum) \
+ : "r" (addr), "Ir" (size), "0" (current_thread_info()->addr_limit) \
+ : "cc"); \
+--
+2.30.1
+
--- /dev/null
+From 2897131264a0f2c96792ab848873f698411331dd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 24 Jan 2019 21:43:40 +0100
+Subject: ARM: 8829/1: spinlock: use unified assembler language syntax
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit eb7ff9023e4f2998d527b37bffe794759800332a upstream.
+
+Convert the conditional infix to a postfix to make sure this inline
+assembly is unified syntax. Since gcc assumes non-unified syntax
+when emitting ARM instructions, make sure to define the syntax as
+unified.
+
+This allows to use LLVM's integrated assembler.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/include/asm/spinlock.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
+index 099c78fcf62d..8f009e788ad4 100644
+--- a/arch/arm/include/asm/spinlock.h
++++ b/arch/arm/include/asm/spinlock.h
+@@ -210,11 +210,12 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
+
+ prefetchw(&rw->lock);
+ __asm__ __volatile__(
++" .syntax unified\n"
+ "1: ldrex %0, [%2]\n"
+ " adds %0, %0, #1\n"
+ " strexpl %1, %0, [%2]\n"
+ WFE("mi")
+-" rsbpls %0, %1, #0\n"
++" rsbspl %0, %1, #0\n"
+ " bmi 1b"
+ : "=&r" (tmp), "=&r" (tmp2)
+ : "r" (&rw->lock)
+--
+2.30.1
+
--- /dev/null
+From e16d94a71959500edc7d27a1720f8243b70d978c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 18 Feb 2019 00:54:36 +0100
+Subject: ARM: 8841/1: use unified assembler in macros
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit a216376add730ec86a8bcee5735f62fd890cb2d0 upstream.
+
+Use unified assembler syntax (UAL) in macros. Divided syntax is
+considered deprecated. This will also allow to build the kernel
+using LLVM's integrated assembler.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Acked-by: Nicolas Pitre <nico@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/lib/copy_from_user.S | 2 +-
+ arch/arm/lib/copy_to_user.S | 2 +-
+ arch/arm/lib/memcpy.S | 4 ++--
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
+index f1e34f16cfab..53b0b4bfead2 100644
+--- a/arch/arm/lib/copy_from_user.S
++++ b/arch/arm/lib/copy_from_user.S
+@@ -70,7 +70,7 @@
+ .endm
+
+ .macro str1b ptr reg cond=al abort
+- str\cond\()b \reg, [\ptr], #1
++ strb\cond \reg, [\ptr], #1
+ .endm
+
+ .macro enter reg1 reg2
+diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
+index 970abe521197..563472d98aa3 100644
+--- a/arch/arm/lib/copy_to_user.S
++++ b/arch/arm/lib/copy_to_user.S
+@@ -54,7 +54,7 @@
+ .endm
+
+ .macro ldr1b ptr reg cond=al abort
+- ldr\cond\()b \reg, [\ptr], #1
++ ldrb\cond \reg, [\ptr], #1
+ .endm
+
+ .macro str1w ptr reg abort
+diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
+index 64111bd4440b..4a6997bb4404 100644
+--- a/arch/arm/lib/memcpy.S
++++ b/arch/arm/lib/memcpy.S
+@@ -30,7 +30,7 @@
+ .endm
+
+ .macro ldr1b ptr reg cond=al abort
+- ldr\cond\()b \reg, [\ptr], #1
++ ldrb\cond \reg, [\ptr], #1
+ .endm
+
+ .macro str1w ptr reg abort
+@@ -42,7 +42,7 @@
+ .endm
+
+ .macro str1b ptr reg cond=al abort
+- str\cond\()b \reg, [\ptr], #1
++ strb\cond \reg, [\ptr], #1
+ .endm
+
+ .macro enter reg1 reg2
+--
+2.30.1
+
--- /dev/null
+From 0a75bd58f00b827008645f516b08b7fe63c21555 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 18 Feb 2019 00:57:38 +0100
+Subject: ARM: 8844/1: use unified assembler in assembly files
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit e44fc38818ed795f4c661d5414c6e0affae0fa63 upstream.
+
+Use unified assembler syntax (UAL) in assembly files. Divided
+syntax is considered deprecated. This will also allow to build
+the kernel using LLVM's integrated assembler.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Acked-by: Nicolas Pitre <nico@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/bootp/init.S | 2 +-
+ arch/arm/boot/compressed/ll_char_wr.S | 4 +-
+ .../include/asm/hardware/entry-macro-iomd.S | 10 ++---
+ arch/arm/include/debug/tegra.S | 2 +-
+ arch/arm/kernel/debug.S | 2 +-
+ arch/arm/kernel/entry-armv.S | 12 +++---
+ arch/arm/kernel/entry-common.S | 2 +-
+ arch/arm/kernel/entry-header.S | 8 ++--
+ arch/arm/lib/clear_user.S | 2 +-
+ arch/arm/lib/copy_page.S | 4 +-
+ arch/arm/lib/copy_template.S | 4 +-
+ arch/arm/lib/csumpartial.S | 20 ++++-----
+ arch/arm/lib/csumpartialcopygeneric.S | 4 +-
+ arch/arm/lib/csumpartialcopyuser.S | 2 +-
+ arch/arm/lib/div64.S | 4 +-
+ arch/arm/lib/floppydma.S | 10 ++---
+ arch/arm/lib/io-readsb.S | 20 ++++-----
+ arch/arm/lib/io-readsl.S | 2 +-
+ arch/arm/lib/io-readsw-armv3.S | 6 +--
+ arch/arm/lib/io-readsw-armv4.S | 12 +++---
+ arch/arm/lib/io-writesb.S | 20 ++++-----
+ arch/arm/lib/io-writesl.S | 2 +-
+ arch/arm/lib/io-writesw-armv3.S | 2 +-
+ arch/arm/lib/io-writesw-armv4.S | 6 +--
+ arch/arm/lib/lib1funcs.S | 4 +-
+ arch/arm/lib/memmove.S | 24 +++++------
+ arch/arm/lib/memset.S | 42 +++++++++----------
+ .../mach-ks8695/include/mach/entry-macro.S | 2 +-
+ arch/arm/mach-tegra/reset-handler.S | 2 +-
+ arch/arm/mm/cache-v6.S | 8 ++--
+ arch/arm/mm/proc-v7m.S | 4 +-
+ 31 files changed, 124 insertions(+), 124 deletions(-)
+
+diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S
+index 78b508075161..142927e5f485 100644
+--- a/arch/arm/boot/bootp/init.S
++++ b/arch/arm/boot/bootp/init.S
+@@ -44,7 +44,7 @@ _start: add lr, pc, #-0x8 @ lr = current load addr
+ */
+ movne r10, #0 @ terminator
+ movne r4, #2 @ Size of this entry (2 words)
+- stmneia r9, {r4, r5, r10} @ Size, ATAG_CORE, terminator
++ stmiane r9, {r4, r5, r10} @ Size, ATAG_CORE, terminator
+
+ /*
+ * find the end of the tag list, and then add an INITRD tag on the end.
+diff --git a/arch/arm/boot/compressed/ll_char_wr.S b/arch/arm/boot/compressed/ll_char_wr.S
+index 8517c8606b4a..b1dcdb9f4030 100644
+--- a/arch/arm/boot/compressed/ll_char_wr.S
++++ b/arch/arm/boot/compressed/ll_char_wr.S
+@@ -75,7 +75,7 @@ Lrow4bpplp:
+ tst r1, #7 @ avoid using r7 directly after
+ str r7, [r0, -r5]!
+ subne r1, r1, #1
+- ldrneb r7, [r6, r1]
++ ldrbne r7, [r6, r1]
+ bne Lrow4bpplp
+ ldmfd sp!, {r4 - r7, pc}
+
+@@ -103,7 +103,7 @@ Lrow8bpplp:
+ sub r0, r0, r5 @ avoid ip
+ stmia r0, {r4, ip}
+ subne r1, r1, #1
+- ldrneb r7, [r6, r1]
++ ldrbne r7, [r6, r1]
+ bne Lrow8bpplp
+ ldmfd sp!, {r4 - r7, pc}
+
+diff --git a/arch/arm/include/asm/hardware/entry-macro-iomd.S b/arch/arm/include/asm/hardware/entry-macro-iomd.S
+index 8c215acd9b57..f7692731e514 100644
+--- a/arch/arm/include/asm/hardware/entry-macro-iomd.S
++++ b/arch/arm/include/asm/hardware/entry-macro-iomd.S
+@@ -16,25 +16,25 @@
+ ldr \tmp, =irq_prio_h
+ teq \irqstat, #0
+ #ifdef IOMD_BASE
+- ldreqb \irqstat, [\base, #IOMD_DMAREQ] @ get dma
++ ldrbeq \irqstat, [\base, #IOMD_DMAREQ] @ get dma
+ addeq \tmp, \tmp, #256 @ irq_prio_h table size
+ teqeq \irqstat, #0
+ bne 2406f
+ #endif
+- ldreqb \irqstat, [\base, #IOMD_IRQREQA] @ get low priority
++ ldrbeq \irqstat, [\base, #IOMD_IRQREQA] @ get low priority
+ addeq \tmp, \tmp, #256 @ irq_prio_d table size
+ teqeq \irqstat, #0
+ #ifdef IOMD_IRQREQC
+- ldreqb \irqstat, [\base, #IOMD_IRQREQC]
++ ldrbeq \irqstat, [\base, #IOMD_IRQREQC]
+ addeq \tmp, \tmp, #256 @ irq_prio_l table size
+ teqeq \irqstat, #0
+ #endif
+ #ifdef IOMD_IRQREQD
+- ldreqb \irqstat, [\base, #IOMD_IRQREQD]
++ ldrbeq \irqstat, [\base, #IOMD_IRQREQD]
+ addeq \tmp, \tmp, #256 @ irq_prio_lc table size
+ teqeq \irqstat, #0
+ #endif
+-2406: ldrneb \irqnr, [\tmp, \irqstat] @ get IRQ number
++2406: ldrbne \irqnr, [\tmp, \irqstat] @ get IRQ number
+ .endm
+
+ /*
+diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
+index 3bc80599c022..4a5a645c76e2 100644
+--- a/arch/arm/include/debug/tegra.S
++++ b/arch/arm/include/debug/tegra.S
+@@ -173,7 +173,7 @@
+
+ .macro senduart, rd, rx
+ cmp \rx, #0
+- strneb \rd, [\rx, #UART_TX << UART_SHIFT]
++ strbne \rd, [\rx, #UART_TX << UART_SHIFT]
+ 1001:
+ .endm
+
+diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
+index b795dc2408c0..b9f94e03d916 100644
+--- a/arch/arm/kernel/debug.S
++++ b/arch/arm/kernel/debug.S
+@@ -86,7 +86,7 @@ hexbuf_rel: .long hexbuf_addr - .
+ ENTRY(printascii)
+ addruart_current r3, r1, r2
+ 1: teq r0, #0
+- ldrneb r1, [r0], #1
++ ldrbne r1, [r0], #1
+ teqne r1, #0
+ reteq lr
+ 2: teq r1, #'\n'
+diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
+index 89e551eebff1..61cba32226e2 100644
+--- a/arch/arm/kernel/entry-armv.S
++++ b/arch/arm/kernel/entry-armv.S
+@@ -629,7 +629,7 @@ call_fpe:
+ @ Test if we need to give access to iWMMXt coprocessors
+ ldr r5, [r10, #TI_FLAGS]
+ rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
+- movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
++ movscs r7, r5, lsr #(TIF_USING_IWMMXT + 1)
+ bcs iwmmxt_task_enable
+ #endif
+ ARM( add pc, pc, r8, lsr #6 )
+@@ -865,7 +865,7 @@ __kuser_cmpxchg64: @ 0xffff0f60
+ smp_dmb arm
+ 1: ldrexd r0, r1, [r2] @ load current val
+ eors r3, r0, r4 @ compare with oldval (1)
+- eoreqs r3, r1, r5 @ compare with oldval (2)
++ eorseq r3, r1, r5 @ compare with oldval (2)
+ strexdeq r3, r6, r7, [r2] @ store newval if eq
+ teqeq r3, #1 @ success?
+ beq 1b @ if no then retry
+@@ -889,8 +889,8 @@ __kuser_cmpxchg64: @ 0xffff0f60
+ ldmia r1, {r6, lr} @ load new val
+ 1: ldmia r2, {r0, r1} @ load current val
+ eors r3, r0, r4 @ compare with oldval (1)
+- eoreqs r3, r1, r5 @ compare with oldval (2)
+-2: stmeqia r2, {r6, lr} @ store newval if eq
++ eorseq r3, r1, r5 @ compare with oldval (2)
++2: stmiaeq r2, {r6, lr} @ store newval if eq
+ rsbs r0, r3, #0 @ set return val and C flag
+ ldmfd sp!, {r4, r5, r6, pc}
+
+@@ -904,7 +904,7 @@ kuser_cmpxchg64_fixup:
+ mov r7, #0xffff0fff
+ sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
+ subs r8, r4, r7
+- rsbcss r8, r8, #(2b - 1b)
++ rsbscs r8, r8, #(2b - 1b)
+ strcs r7, [sp, #S_PC]
+ #if __LINUX_ARM_ARCH__ < 6
+ bcc kuser_cmpxchg32_fixup
+@@ -962,7 +962,7 @@ kuser_cmpxchg32_fixup:
+ mov r7, #0xffff0fff
+ sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
+ subs r8, r4, r7
+- rsbcss r8, r8, #(2b - 1b)
++ rsbscs r8, r8, #(2b - 1b)
+ strcs r7, [sp, #S_PC]
+ ret lr
+ .previous
+diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
+index 0465d65d23de..f7649adef505 100644
+--- a/arch/arm/kernel/entry-common.S
++++ b/arch/arm/kernel/entry-common.S
+@@ -373,7 +373,7 @@ sys_syscall:
+ movhs scno, #0
+ csdb
+ #endif
+- stmloia sp, {r5, r6} @ shuffle args
++ stmialo sp, {r5, r6} @ shuffle args
+ movlo r0, r1
+ movlo r1, r2
+ movlo r2, r3
+diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
+index 7b595f2d4a28..40db0f9188b6 100644
+--- a/arch/arm/kernel/entry-header.S
++++ b/arch/arm/kernel/entry-header.S
+@@ -385,8 +385,8 @@
+ badr lr, \ret @ return address
+ .if \reload
+ add r1, sp, #S_R0 + S_OFF @ pointer to regs
+- ldmccia r1, {r0 - r6} @ reload r0-r6
+- stmccia sp, {r4, r5} @ update stack arguments
++ ldmiacc r1, {r0 - r6} @ reload r0-r6
++ stmiacc sp, {r4, r5} @ update stack arguments
+ .endif
+ ldrcc pc, [\table, \tmp, lsl #2] @ call sys_* routine
+ #else
+@@ -394,8 +394,8 @@
+ badr lr, \ret @ return address
+ .if \reload
+ add r1, sp, #S_R0 + S_OFF @ pointer to regs
+- ldmccia r1, {r0 - r6} @ reload r0-r6
+- stmccia sp, {r4, r5} @ update stack arguments
++ ldmiacc r1, {r0 - r6} @ reload r0-r6
++ stmiacc sp, {r4, r5} @ update stack arguments
+ .endif
+ ldrcc pc, [\table, \nr, lsl #2] @ call sys_* routine
+ #endif
+diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
+index e936352ccb00..55946e3fa2ba 100644
+--- a/arch/arm/lib/clear_user.S
++++ b/arch/arm/lib/clear_user.S
+@@ -44,7 +44,7 @@ UNWIND(.save {r1, lr})
+ strusr r2, r0, 1, ne, rept=2
+ tst r1, #1 @ x1 x0 x1 x0 x1 x0 x1
+ it ne @ explicit IT needed for the label
+-USER( strnebt r2, [r0])
++USER( strbtne r2, [r0])
+ mov r0, #0
+ ldmfd sp!, {r1, pc}
+ UNWIND(.fnend)
+diff --git a/arch/arm/lib/copy_page.S b/arch/arm/lib/copy_page.S
+index 6ee2f6706f86..b84ce1792043 100644
+--- a/arch/arm/lib/copy_page.S
++++ b/arch/arm/lib/copy_page.S
+@@ -39,9 +39,9 @@ ENTRY(copy_page)
+ .endr
+ subs r2, r2, #1 @ 1
+ stmia r0!, {r3, r4, ip, lr} @ 4
+- ldmgtia r1!, {r3, r4, ip, lr} @ 4
++ ldmiagt r1!, {r3, r4, ip, lr} @ 4
+ bgt 1b @ 1
+- PLD( ldmeqia r1!, {r3, r4, ip, lr} )
++ PLD( ldmiaeq r1!, {r3, r4, ip, lr} )
+ PLD( beq 2b )
+ ldmfd sp!, {r4, pc} @ 3
+ ENDPROC(copy_page)
+diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
+index 2d54491b0e22..a11f2c25e03a 100644
+--- a/arch/arm/lib/copy_template.S
++++ b/arch/arm/lib/copy_template.S
+@@ -99,7 +99,7 @@
+
+ CALGN( ands ip, r0, #31 )
+ CALGN( rsb r3, ip, #32 )
+- CALGN( sbcnes r4, r3, r2 ) @ C is always set here
++ CALGN( sbcsne r4, r3, r2 ) @ C is always set here
+ CALGN( bcs 2f )
+ CALGN( adr r4, 6f )
+ CALGN( subs r2, r2, r3 ) @ C gets set
+@@ -204,7 +204,7 @@
+
+ CALGN( ands ip, r0, #31 )
+ CALGN( rsb ip, ip, #32 )
+- CALGN( sbcnes r4, ip, r2 ) @ C is always set here
++ CALGN( sbcsne r4, ip, r2 ) @ C is always set here
+ CALGN( subcc r2, r2, ip )
+ CALGN( bcc 15f )
+
+diff --git a/arch/arm/lib/csumpartial.S b/arch/arm/lib/csumpartial.S
+index 984e0f29d548..bd84e2db353b 100644
+--- a/arch/arm/lib/csumpartial.S
++++ b/arch/arm/lib/csumpartial.S
+@@ -40,9 +40,9 @@ td3 .req lr
+ /* we must have at least one byte. */
+ tst buf, #1 @ odd address?
+ movne sum, sum, ror #8
+- ldrneb td0, [buf], #1
++ ldrbne td0, [buf], #1
+ subne len, len, #1
+- adcnes sum, sum, td0, put_byte_1
++ adcsne sum, sum, td0, put_byte_1
+
+ .Lless4: tst len, #6
+ beq .Lless8_byte
+@@ -68,8 +68,8 @@ td3 .req lr
+ bne .Lless8_wordlp
+
+ .Lless8_byte: tst len, #1 @ odd number of bytes
+- ldrneb td0, [buf], #1 @ include last byte
+- adcnes sum, sum, td0, put_byte_0 @ update checksum
++ ldrbne td0, [buf], #1 @ include last byte
++ adcsne sum, sum, td0, put_byte_0 @ update checksum
+
+ .Ldone: adc r0, sum, #0 @ collect up the last carry
+ ldr td0, [sp], #4
+@@ -78,17 +78,17 @@ td3 .req lr
+ ldr pc, [sp], #4 @ return
+
+ .Lnot_aligned: tst buf, #1 @ odd address
+- ldrneb td0, [buf], #1 @ make even
++ ldrbne td0, [buf], #1 @ make even
+ subne len, len, #1
+- adcnes sum, sum, td0, put_byte_1 @ update checksum
++ adcsne sum, sum, td0, put_byte_1 @ update checksum
+
+ tst buf, #2 @ 32-bit aligned?
+ #if __LINUX_ARM_ARCH__ >= 4
+- ldrneh td0, [buf], #2 @ make 32-bit aligned
++ ldrhne td0, [buf], #2 @ make 32-bit aligned
+ subne len, len, #2
+ #else
+- ldrneb td0, [buf], #1
+- ldrneb ip, [buf], #1
++ ldrbne td0, [buf], #1
++ ldrbne ip, [buf], #1
+ subne len, len, #2
+ #ifndef __ARMEB__
+ orrne td0, td0, ip, lsl #8
+@@ -96,7 +96,7 @@ td3 .req lr
+ orrne td0, ip, td0, lsl #8
+ #endif
+ #endif
+- adcnes sum, sum, td0 @ update checksum
++ adcsne sum, sum, td0 @ update checksum
+ ret lr
+
+ ENTRY(csum_partial)
+diff --git a/arch/arm/lib/csumpartialcopygeneric.S b/arch/arm/lib/csumpartialcopygeneric.S
+index 10b45909610c..08e17758cbea 100644
+--- a/arch/arm/lib/csumpartialcopygeneric.S
++++ b/arch/arm/lib/csumpartialcopygeneric.S
+@@ -148,9 +148,9 @@ FN_ENTRY
+ strb r5, [dst], #1
+ mov r5, r4, get_byte_2
+ .Lexit: tst len, #1
+- strneb r5, [dst], #1
++ strbne r5, [dst], #1
+ andne r5, r5, #255
+- adcnes sum, sum, r5, put_byte_0
++ adcsne sum, sum, r5, put_byte_0
+
+ /*
+ * If the dst pointer was not 16-bit aligned, we
+diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
+index b83fdc06286a..f4716d98e0b4 100644
+--- a/arch/arm/lib/csumpartialcopyuser.S
++++ b/arch/arm/lib/csumpartialcopyuser.S
+@@ -95,7 +95,7 @@
+ add r2, r2, r1
+ mov r0, #0 @ zero the buffer
+ 9002: teq r2, r1
+- strneb r0, [r1], #1
++ strbne r0, [r1], #1
+ bne 9002b
+ load_regs
+ .popsection
+diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
+index a9eafe4981eb..4d80f690c48b 100644
+--- a/arch/arm/lib/div64.S
++++ b/arch/arm/lib/div64.S
+@@ -88,8 +88,8 @@ UNWIND(.fnstart)
+ @ Break out early if dividend reaches 0.
+ 2: cmp xh, yl
+ orrcs yh, yh, ip
+- subcss xh, xh, yl
+- movnes ip, ip, lsr #1
++ subscs xh, xh, yl
++ movsne ip, ip, lsr #1
+ mov yl, yl, lsr #1
+ bne 2b
+
+diff --git a/arch/arm/lib/floppydma.S b/arch/arm/lib/floppydma.S
+index 617150b1baef..de68d3b343e3 100644
+--- a/arch/arm/lib/floppydma.S
++++ b/arch/arm/lib/floppydma.S
+@@ -14,8 +14,8 @@
+ .global floppy_fiqin_end
+ ENTRY(floppy_fiqin_start)
+ subs r9, r9, #1
+- ldrgtb r12, [r11, #-4]
+- ldrleb r12, [r11], #0
++ ldrbgt r12, [r11, #-4]
++ ldrble r12, [r11], #0
+ strb r12, [r10], #1
+ subs pc, lr, #4
+ floppy_fiqin_end:
+@@ -23,10 +23,10 @@ floppy_fiqin_end:
+ .global floppy_fiqout_end
+ ENTRY(floppy_fiqout_start)
+ subs r9, r9, #1
+- ldrgeb r12, [r10], #1
++ ldrbge r12, [r10], #1
+ movlt r12, #0
+- strleb r12, [r11], #0
+- subles pc, lr, #4
++ strble r12, [r11], #0
++ subsle pc, lr, #4
+ strb r12, [r11, #-4]
+ subs pc, lr, #4
+ floppy_fiqout_end:
+diff --git a/arch/arm/lib/io-readsb.S b/arch/arm/lib/io-readsb.S
+index c31b2f3153f1..91038a0a77b5 100644
+--- a/arch/arm/lib/io-readsb.S
++++ b/arch/arm/lib/io-readsb.S
+@@ -16,10 +16,10 @@
+ cmp ip, #2
+ ldrb r3, [r0]
+ strb r3, [r1], #1
+- ldrgeb r3, [r0]
+- strgeb r3, [r1], #1
+- ldrgtb r3, [r0]
+- strgtb r3, [r1], #1
++ ldrbge r3, [r0]
++ strbge r3, [r1], #1
++ ldrbgt r3, [r0]
++ strbgt r3, [r1], #1
+ subs r2, r2, ip
+ bne .Linsb_aligned
+
+@@ -72,7 +72,7 @@ ENTRY(__raw_readsb)
+ bpl .Linsb_16_lp
+
+ tst r2, #15
+- ldmeqfd sp!, {r4 - r6, pc}
++ ldmfdeq sp!, {r4 - r6, pc}
+
+ .Linsb_no_16: tst r2, #8
+ beq .Linsb_no_8
+@@ -109,15 +109,15 @@ ENTRY(__raw_readsb)
+ str r3, [r1], #4
+
+ .Linsb_no_4: ands r2, r2, #3
+- ldmeqfd sp!, {r4 - r6, pc}
++ ldmfdeq sp!, {r4 - r6, pc}
+
+ cmp r2, #2
+ ldrb r3, [r0]
+ strb r3, [r1], #1
+- ldrgeb r3, [r0]
+- strgeb r3, [r1], #1
+- ldrgtb r3, [r0]
+- strgtb r3, [r1]
++ ldrbge r3, [r0]
++ strbge r3, [r1], #1
++ ldrbgt r3, [r0]
++ strbgt r3, [r1]
+
+ ldmfd sp!, {r4 - r6, pc}
+ ENDPROC(__raw_readsb)
+diff --git a/arch/arm/lib/io-readsl.S b/arch/arm/lib/io-readsl.S
+index 2ed86fa5465f..f2e2064318d2 100644
+--- a/arch/arm/lib/io-readsl.S
++++ b/arch/arm/lib/io-readsl.S
+@@ -30,7 +30,7 @@ ENTRY(__raw_readsl)
+ 2: movs r2, r2, lsl #31
+ ldrcs r3, [r0, #0]
+ ldrcs ip, [r0, #0]
+- stmcsia r1!, {r3, ip}
++ stmiacs r1!, {r3, ip}
+ ldrne r3, [r0, #0]
+ strne r3, [r1, #0]
+ ret lr
+diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S
+index 413da9914529..8b25b69c516e 100644
+--- a/arch/arm/lib/io-readsw-armv3.S
++++ b/arch/arm/lib/io-readsw-armv3.S
+@@ -68,7 +68,7 @@ ENTRY(__raw_readsw)
+ bpl .Linsw_8_lp
+
+ tst r2, #7
+- ldmeqfd sp!, {r4, r5, r6, pc}
++ ldmfdeq sp!, {r4, r5, r6, pc}
+
+ .Lno_insw_8: tst r2, #4
+ beq .Lno_insw_4
+@@ -97,9 +97,9 @@ ENTRY(__raw_readsw)
+
+ .Lno_insw_2: tst r2, #1
+ ldrne r3, [r0]
+- strneb r3, [r1], #1
++ strbne r3, [r1], #1
+ movne r3, r3, lsr #8
+- strneb r3, [r1]
++ strbne r3, [r1]
+
+ ldmfd sp!, {r4, r5, r6, pc}
+
+diff --git a/arch/arm/lib/io-readsw-armv4.S b/arch/arm/lib/io-readsw-armv4.S
+index d9a45e9692ae..5efdd66f5dcd 100644
+--- a/arch/arm/lib/io-readsw-armv4.S
++++ b/arch/arm/lib/io-readsw-armv4.S
+@@ -76,8 +76,8 @@ ENTRY(__raw_readsw)
+ pack r3, r3, ip
+ str r3, [r1], #4
+
+-.Lno_insw_2: ldrneh r3, [r0]
+- strneh r3, [r1]
++.Lno_insw_2: ldrhne r3, [r0]
++ strhne r3, [r1]
+
+ ldmfd sp!, {r4, r5, pc}
+
+@@ -94,7 +94,7 @@ ENTRY(__raw_readsw)
+ #endif
+
+ .Linsw_noalign: stmfd sp!, {r4, lr}
+- ldrccb ip, [r1, #-1]!
++ ldrbcc ip, [r1, #-1]!
+ bcc 1f
+
+ ldrh ip, [r0]
+@@ -121,11 +121,11 @@ ENTRY(__raw_readsw)
+
+ 3: tst r2, #1
+ strb ip, [r1], #1
+- ldrneh ip, [r0]
++ ldrhne ip, [r0]
+ _BE_ONLY_( movne ip, ip, ror #8 )
+- strneb ip, [r1], #1
++ strbne ip, [r1], #1
+ _LE_ONLY_( movne ip, ip, lsr #8 )
+ _BE_ONLY_( movne ip, ip, lsr #24 )
+- strneb ip, [r1]
++ strbne ip, [r1]
+ ldmfd sp!, {r4, pc}
+ ENDPROC(__raw_readsw)
+diff --git a/arch/arm/lib/io-writesb.S b/arch/arm/lib/io-writesb.S
+index a46bbc9b168b..7d2881a2381e 100644
+--- a/arch/arm/lib/io-writesb.S
++++ b/arch/arm/lib/io-writesb.S
+@@ -36,10 +36,10 @@
+ cmp ip, #2
+ ldrb r3, [r1], #1
+ strb r3, [r0]
+- ldrgeb r3, [r1], #1
+- strgeb r3, [r0]
+- ldrgtb r3, [r1], #1
+- strgtb r3, [r0]
++ ldrbge r3, [r1], #1
++ strbge r3, [r0]
++ ldrbgt r3, [r1], #1
++ strbgt r3, [r0]
+ subs r2, r2, ip
+ bne .Loutsb_aligned
+
+@@ -64,7 +64,7 @@ ENTRY(__raw_writesb)
+ bpl .Loutsb_16_lp
+
+ tst r2, #15
+- ldmeqfd sp!, {r4, r5, pc}
++ ldmfdeq sp!, {r4, r5, pc}
+
+ .Loutsb_no_16: tst r2, #8
+ beq .Loutsb_no_8
+@@ -80,15 +80,15 @@ ENTRY(__raw_writesb)
+ outword r3
+
+ .Loutsb_no_4: ands r2, r2, #3
+- ldmeqfd sp!, {r4, r5, pc}
++ ldmfdeq sp!, {r4, r5, pc}
+
+ cmp r2, #2
+ ldrb r3, [r1], #1
+ strb r3, [r0]
+- ldrgeb r3, [r1], #1
+- strgeb r3, [r0]
+- ldrgtb r3, [r1]
+- strgtb r3, [r0]
++ ldrbge r3, [r1], #1
++ strbge r3, [r0]
++ ldrbgt r3, [r1]
++ strbgt r3, [r0]
+
+ ldmfd sp!, {r4, r5, pc}
+ ENDPROC(__raw_writesb)
+diff --git a/arch/arm/lib/io-writesl.S b/arch/arm/lib/io-writesl.S
+index 4ea2435988c1..7596ac0c90b0 100644
+--- a/arch/arm/lib/io-writesl.S
++++ b/arch/arm/lib/io-writesl.S
+@@ -28,7 +28,7 @@ ENTRY(__raw_writesl)
+ bpl 1b
+ ldmfd sp!, {r4, lr}
+ 2: movs r2, r2, lsl #31
+- ldmcsia r1!, {r3, ip}
++ ldmiacs r1!, {r3, ip}
+ strcs r3, [r0, #0]
+ ldrne r3, [r1, #0]
+ strcs ip, [r0, #0]
+diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
+index 121789eb6802..cb94b9b49405 100644
+--- a/arch/arm/lib/io-writesw-armv3.S
++++ b/arch/arm/lib/io-writesw-armv3.S
+@@ -79,7 +79,7 @@ ENTRY(__raw_writesw)
+ bpl .Loutsw_8_lp
+
+ tst r2, #7
+- ldmeqfd sp!, {r4, r5, r6, pc}
++ ldmfdeq sp!, {r4, r5, r6, pc}
+
+ .Lno_outsw_8: tst r2, #4
+ beq .Lno_outsw_4
+diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
+index 269f90c51ad2..e6645b2f249e 100644
+--- a/arch/arm/lib/io-writesw-armv4.S
++++ b/arch/arm/lib/io-writesw-armv4.S
+@@ -61,8 +61,8 @@ ENTRY(__raw_writesw)
+ ldr r3, [r1], #4
+ outword r3
+
+-.Lno_outsw_2: ldrneh r3, [r1]
+- strneh r3, [r0]
++.Lno_outsw_2: ldrhne r3, [r1]
++ strhne r3, [r0]
+
+ ldmfd sp!, {r4, r5, pc}
+
+@@ -95,6 +95,6 @@ ENTRY(__raw_writesw)
+
+ tst r2, #1
+ 3: movne ip, r3, lsr #8
+- strneh ip, [r0]
++ strhne ip, [r0]
+ ret lr
+ ENDPROC(__raw_writesw)
+diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
+index 9397b2e532af..c23f9d9e2970 100644
+--- a/arch/arm/lib/lib1funcs.S
++++ b/arch/arm/lib/lib1funcs.S
+@@ -96,7 +96,7 @@ Boston, MA 02111-1307, USA. */
+ subhs \dividend, \dividend, \divisor, lsr #3
+ orrhs \result, \result, \curbit, lsr #3
+ cmp \dividend, #0 @ Early termination?
+- movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
++ movsne \curbit, \curbit, lsr #4 @ No, any more bits to do?
+ movne \divisor, \divisor, lsr #4
+ bne 1b
+
+@@ -182,7 +182,7 @@ Boston, MA 02111-1307, USA. */
+ subhs \dividend, \dividend, \divisor, lsr #3
+ cmp \dividend, #1
+ mov \divisor, \divisor, lsr #4
+- subges \order, \order, #4
++ subsge \order, \order, #4
+ bge 1b
+
+ tst \order, #3
+diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
+index 69a9d47fc5ab..d70304cb2cd0 100644
+--- a/arch/arm/lib/memmove.S
++++ b/arch/arm/lib/memmove.S
+@@ -59,7 +59,7 @@ ENTRY(memmove)
+ blt 5f
+
+ CALGN( ands ip, r0, #31 )
+- CALGN( sbcnes r4, ip, r2 ) @ C is always set here
++ CALGN( sbcsne r4, ip, r2 ) @ C is always set here
+ CALGN( bcs 2f )
+ CALGN( adr r4, 6f )
+ CALGN( subs r2, r2, ip ) @ C is set here
+@@ -114,20 +114,20 @@ ENTRY(memmove)
+ UNWIND( .save {r0, r4, lr} ) @ still in first stmfd block
+
+ 8: movs r2, r2, lsl #31
+- ldrneb r3, [r1, #-1]!
+- ldrcsb r4, [r1, #-1]!
+- ldrcsb ip, [r1, #-1]
+- strneb r3, [r0, #-1]!
+- strcsb r4, [r0, #-1]!
+- strcsb ip, [r0, #-1]
++ ldrbne r3, [r1, #-1]!
++ ldrbcs r4, [r1, #-1]!
++ ldrbcs ip, [r1, #-1]
++ strbne r3, [r0, #-1]!
++ strbcs r4, [r0, #-1]!
++ strbcs ip, [r0, #-1]
+ ldmfd sp!, {r0, r4, pc}
+
+ 9: cmp ip, #2
+- ldrgtb r3, [r1, #-1]!
+- ldrgeb r4, [r1, #-1]!
++ ldrbgt r3, [r1, #-1]!
++ ldrbge r4, [r1, #-1]!
+ ldrb lr, [r1, #-1]!
+- strgtb r3, [r0, #-1]!
+- strgeb r4, [r0, #-1]!
++ strbgt r3, [r0, #-1]!
++ strbge r4, [r0, #-1]!
+ subs r2, r2, ip
+ strb lr, [r0, #-1]!
+ blt 8b
+@@ -150,7 +150,7 @@ ENTRY(memmove)
+ blt 14f
+
+ CALGN( ands ip, r0, #31 )
+- CALGN( sbcnes r4, ip, r2 ) @ C is always set here
++ CALGN( sbcsne r4, ip, r2 ) @ C is always set here
+ CALGN( subcc r2, r2, ip )
+ CALGN( bcc 15f )
+
+diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
+index ed6d35d9cdb5..5593a45e0a8c 100644
+--- a/arch/arm/lib/memset.S
++++ b/arch/arm/lib/memset.S
+@@ -44,20 +44,20 @@ UNWIND( .save {r8, lr} )
+ mov lr, r3
+
+ 2: subs r2, r2, #64
+- stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
+- stmgeia ip!, {r1, r3, r8, lr}
+- stmgeia ip!, {r1, r3, r8, lr}
+- stmgeia ip!, {r1, r3, r8, lr}
++ stmiage ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
++ stmiage ip!, {r1, r3, r8, lr}
++ stmiage ip!, {r1, r3, r8, lr}
++ stmiage ip!, {r1, r3, r8, lr}
+ bgt 2b
+- ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
++ ldmfdeq sp!, {r8, pc} @ Now <64 bytes to go.
+ /*
+ * No need to correct the count; we're only testing bits from now on
+ */
+ tst r2, #32
+- stmneia ip!, {r1, r3, r8, lr}
+- stmneia ip!, {r1, r3, r8, lr}
++ stmiane ip!, {r1, r3, r8, lr}
++ stmiane ip!, {r1, r3, r8, lr}
+ tst r2, #16
+- stmneia ip!, {r1, r3, r8, lr}
++ stmiane ip!, {r1, r3, r8, lr}
+ ldmfd sp!, {r8, lr}
+ UNWIND( .fnend )
+
+@@ -87,22 +87,22 @@ UNWIND( .save {r4-r8, lr} )
+ rsb r8, r8, #32
+ sub r2, r2, r8
+ movs r8, r8, lsl #(32 - 4)
+- stmcsia ip!, {r4, r5, r6, r7}
+- stmmiia ip!, {r4, r5}
++ stmiacs ip!, {r4, r5, r6, r7}
++ stmiami ip!, {r4, r5}
+ tst r8, #(1 << 30)
+ mov r8, r1
+ strne r1, [ip], #4
+
+ 3: subs r2, r2, #64
+- stmgeia ip!, {r1, r3-r8, lr}
+- stmgeia ip!, {r1, r3-r8, lr}
++ stmiage ip!, {r1, r3-r8, lr}
++ stmiage ip!, {r1, r3-r8, lr}
+ bgt 3b
+- ldmeqfd sp!, {r4-r8, pc}
++ ldmfdeq sp!, {r4-r8, pc}
+
+ tst r2, #32
+- stmneia ip!, {r1, r3-r8, lr}
++ stmiane ip!, {r1, r3-r8, lr}
+ tst r2, #16
+- stmneia ip!, {r4-r7}
++ stmiane ip!, {r4-r7}
+ ldmfd sp!, {r4-r8, lr}
+ UNWIND( .fnend )
+
+@@ -110,7 +110,7 @@ UNWIND( .fnend )
+
+ UNWIND( .fnstart )
+ 4: tst r2, #8
+- stmneia ip!, {r1, r3}
++ stmiane ip!, {r1, r3}
+ tst r2, #4
+ strne r1, [ip], #4
+ /*
+@@ -118,17 +118,17 @@ UNWIND( .fnstart )
+ * may have an unaligned pointer as well.
+ */
+ 5: tst r2, #2
+- strneb r1, [ip], #1
+- strneb r1, [ip], #1
++ strbne r1, [ip], #1
++ strbne r1, [ip], #1
+ tst r2, #1
+- strneb r1, [ip], #1
++ strbne r1, [ip], #1
+ ret lr
+
+ 6: subs r2, r2, #4 @ 1 do we have enough
+ blt 5b @ 1 bytes to align with?
+ cmp r3, #2 @ 1
+- strltb r1, [ip], #1 @ 1
+- strleb r1, [ip], #1 @ 1
++ strblt r1, [ip], #1 @ 1
++ strble r1, [ip], #1 @ 1
+ strb r1, [ip], #1 @ 1
+ add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
+ b 1b
+diff --git a/arch/arm/mach-ks8695/include/mach/entry-macro.S b/arch/arm/mach-ks8695/include/mach/entry-macro.S
+index 8315b34f32ff..7ff812cb010b 100644
+--- a/arch/arm/mach-ks8695/include/mach/entry-macro.S
++++ b/arch/arm/mach-ks8695/include/mach/entry-macro.S
+@@ -42,6 +42,6 @@
+ moveq \irqstat, \irqstat, lsr #2
+ addeq \irqnr, \irqnr, #2
+ tst \irqstat, #0x01
+- addeqs \irqnr, \irqnr, #1
++ addseq \irqnr, \irqnr, #1
+ 1001:
+ .endm
+diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
+index e31f167a8199..de9485e28ff0 100644
+--- a/arch/arm/mach-tegra/reset-handler.S
++++ b/arch/arm/mach-tegra/reset-handler.S
+@@ -172,7 +172,7 @@ after_errata:
+ mov32 r5, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET
+ mov r0, #CPU_NOT_RESETTABLE
+ cmp r10, #0
+- strneb r0, [r5, #__tegra20_cpu1_resettable_status_offset]
++ strbne r0, [r5, #__tegra20_cpu1_resettable_status_offset]
+ 1:
+ #endif
+
+diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
+index 24659952c278..be68d62566c7 100644
+--- a/arch/arm/mm/cache-v6.S
++++ b/arch/arm/mm/cache-v6.S
+@@ -215,8 +215,8 @@ v6_dma_inv_range:
+ #endif
+ tst r1, #D_CACHE_LINE_SIZE - 1
+ #ifdef CONFIG_DMA_CACHE_RWFO
+- ldrneb r2, [r1, #-1] @ read for ownership
+- strneb r2, [r1, #-1] @ write for ownership
++ ldrbne r2, [r1, #-1] @ read for ownership
++ strbne r2, [r1, #-1] @ write for ownership
+ #endif
+ bic r1, r1, #D_CACHE_LINE_SIZE - 1
+ #ifdef HARVARD_CACHE
+@@ -284,8 +284,8 @@ ENTRY(v6_dma_flush_range)
+ add r0, r0, #D_CACHE_LINE_SIZE
+ cmp r0, r1
+ #ifdef CONFIG_DMA_CACHE_RWFO
+- ldrlob r2, [r0] @ read for ownership
+- strlob r2, [r0] @ write for ownership
++ ldrblo r2, [r0] @ read for ownership
++ strblo r2, [r0] @ write for ownership
+ #endif
+ blo 1b
+ mov r0, #0
+diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
+index 9c2978c128d9..293a4325b459 100644
+--- a/arch/arm/mm/proc-v7m.S
++++ b/arch/arm/mm/proc-v7m.S
+@@ -150,10 +150,10 @@ __v7m_setup_cont:
+
+ @ Configure caches (if implemented)
+ teq r8, #0
+- stmneia sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
++ stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
+ blne v7m_invalidate_l1
+ teq r8, #0 @ re-evalutae condition
+- ldmneia sp, {r0-r6, lr}
++ ldmiane sp, {r0-r6, lr}
+
+ @ Configure the System Control Register to ensure 8-byte stack alignment
+ @ Note the STKALIGN bit is either RW or RAO.
+--
+2.30.1
+
--- /dev/null
+From c23fa54ef1b9cb7457cd037d9c6cfb611242e834 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 23 Mar 2019 12:10:44 +0100
+Subject: ARM: 8852/1: uaccess: use unified assembler language syntax
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit fe09d9c641f2064390afabdf436fe09b35e075ff upstream.
+
+Convert the conditional infix to a postfix to make sure this inline
+assembly is unified syntax. Since gcc assumes non-unified syntax
+when emitting ARM instructions, make sure to define the syntax as
+unified.
+
+This allows to use LLVM's integrated assembler.
+
+Additionally, for GCC ".syntax unified" for inline assembly.
+When compiling non-Thumb2 GCC always emits a ".syntax divided"
+at the beginning of the inline assembly which makes the
+assembler fail. Since GCC 5 there is the -masm-syntax-unified
+GCC option which make GCC assume unified syntax asm and hence
+emits ".syntax unified" even in ARM mode. However, the option
+is broken since GCC version 6 (see GCC PR88648 [1]). Work
+around by adding ".syntax unified" as part of the inline
+assembly.
+
+[0] https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html#index-masm-syntax-unified
+[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88648
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/include/asm/uaccess.h | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
+index a50f9b4e2574..14827d583e26 100644
+--- a/arch/arm/include/asm/uaccess.h
++++ b/arch/arm/include/asm/uaccess.h
+@@ -113,10 +113,11 @@ static inline void __user *__uaccess_mask_range_ptr(const void __user *ptr,
+ unsigned long tmp;
+
+ asm volatile(
++ " .syntax unified\n"
+ " sub %1, %3, #1\n"
+ " subs %1, %1, %0\n"
+ " addhs %1, %1, #1\n"
+- " subhss %1, %1, %2\n"
++ " subshs %1, %1, %2\n"
+ " movlo %0, #0\n"
+ : "+r" (safe_ptr), "=&r" (tmp)
+ : "r" (size), "r" (current_thread_info()->addr_limit)
+--
+2.30.1
+
--- /dev/null
+From ba342caba10bd49819b29e610ca5000646884aee Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 3 Nov 2019 19:22:06 +0100
+Subject: ARM: 8929/1: use APSR_nzcv instead of r15 as mrc operand
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit 9f1984c6ae30e2a379751339ce3375a21099b5d4 upstream.
+
+LLVM's integrated assembler does not accept r15 as mrc operand.
+ arch/arm/boot/compressed/head.S:1267:16: error: operand must be a register in range [r0, r14] or apsr_nzcv
+ 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
+ ^
+
+Use APSR_nzcv instead of r15. The GNU assembler supports this
+syntax since binutils 2.21 [0].
+
+[0] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=db472d6ff0f438a21b357249a9b48e4b74498076
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/compressed/head.S | 2 +-
+ arch/arm/mm/proc-arm1026.S | 4 ++--
+ arch/arm/mm/proc-arm926.S | 4 ++--
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
+index 69e661f574a0..9d5f9c099ba3 100644
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -1221,7 +1221,7 @@ iflush:
+ __armv5tej_mmu_cache_flush:
+ tst r4, #1
+ movne pc, lr
+-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
+ bne 1b
+ mcr p15, 0, r0, c7, c5, 0 @ flush I cache
+ mcr p15, 0, r0, c7, c10, 4 @ drain WB
+diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
+index 0b37b2cef9d3..72a5dafb8db6 100644
+--- a/arch/arm/mm/proc-arm1026.S
++++ b/arch/arm/mm/proc-arm1026.S
+@@ -143,7 +143,7 @@ ENTRY(arm1026_flush_kern_cache_all)
+ mov ip, #0
+ __flush_whole_cache:
+ #ifndef CONFIG_CPU_DCACHE_DISABLE
+-1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
+ bne 1b
+ #endif
+ tst r2, #VM_EXEC
+@@ -368,7 +368,7 @@ ENTRY(cpu_arm1026_switch_mm)
+ #ifdef CONFIG_MMU
+ mov r1, #0
+ #ifndef CONFIG_CPU_DCACHE_DISABLE
+-1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
+ bne 1b
+ #endif
+ #ifndef CONFIG_CPU_ICACHE_DISABLE
+diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
+index fb827c633693..96ea567d1b64 100644
+--- a/arch/arm/mm/proc-arm926.S
++++ b/arch/arm/mm/proc-arm926.S
+@@ -145,7 +145,7 @@ __flush_whole_cache:
+ #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+ mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
+ #else
+-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
+ bne 1b
+ #endif
+ tst r2, #VM_EXEC
+@@ -372,7 +372,7 @@ ENTRY(cpu_arm926_switch_mm)
+ mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
+ #else
+ @ && 'Clean & Invalidate whole DCache'
+-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
++1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
+ bne 1b
+ #endif
+ mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
+--
+2.30.1
+
--- /dev/null
+From 938e683ccabc01efe2624dc7ebf70a4485bd50b4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Nov 2019 19:31:45 +0100
+Subject: ARM: 8933/1: replace Sun/Solaris style flag on section directive
+
+From: Nick Desaulniers <ndesaulniers@google.com>
+
+commit 790756c7e0229dedc83bf058ac69633045b1000e upstream.
+
+It looks like a section directive was using "Solaris style" to declare
+the section flags. Replace this with the GNU style so that Clang's
+integrated assembler can assemble this directive.
+
+The modified instances were identified via:
+$ ag \.section | grep #
+
+Link: https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html#SEC119
+Link: https://github.com/ClangBuiltLinux/linux/issues/744
+Link: https://bugs.llvm.org/show_bug.cgi?id=43759
+Link: https://reviews.llvm.org/D69296
+
+Acked-by: Nicolas Pitre <nico@fluxnic.net>
+Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
+Reviewed-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Suggested-by: Fangrui Song <maskray@google.com>
+Suggested-by: Jian Cai <jiancai@google.com>
+Suggested-by: Peter Smith <peter.smith@linaro.org>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/bootp/init.S | 2 +-
+ arch/arm/boot/compressed/big-endian.S | 2 +-
+ arch/arm/boot/compressed/head.S | 2 +-
+ arch/arm/boot/compressed/piggy.S | 2 +-
+ arch/arm/mm/proc-arm1020.S | 2 +-
+ arch/arm/mm/proc-arm1020e.S | 2 +-
+ arch/arm/mm/proc-arm1022.S | 2 +-
+ arch/arm/mm/proc-arm1026.S | 2 +-
+ arch/arm/mm/proc-arm720.S | 2 +-
+ arch/arm/mm/proc-arm740.S | 2 +-
+ arch/arm/mm/proc-arm7tdmi.S | 2 +-
+ arch/arm/mm/proc-arm920.S | 2 +-
+ arch/arm/mm/proc-arm922.S | 2 +-
+ arch/arm/mm/proc-arm925.S | 2 +-
+ arch/arm/mm/proc-arm926.S | 2 +-
+ arch/arm/mm/proc-arm940.S | 2 +-
+ arch/arm/mm/proc-arm946.S | 2 +-
+ arch/arm/mm/proc-arm9tdmi.S | 2 +-
+ arch/arm/mm/proc-fa526.S | 2 +-
+ arch/arm/mm/proc-feroceon.S | 2 +-
+ arch/arm/mm/proc-mohawk.S | 2 +-
+ arch/arm/mm/proc-sa110.S | 2 +-
+ arch/arm/mm/proc-sa1100.S | 2 +-
+ arch/arm/mm/proc-v6.S | 2 +-
+ arch/arm/mm/proc-v7.S | 2 +-
+ arch/arm/mm/proc-v7m.S | 4 ++--
+ arch/arm/mm/proc-xsc3.S | 2 +-
+ arch/arm/mm/proc-xscale.S | 2 +-
+ 28 files changed, 29 insertions(+), 29 deletions(-)
+
+diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S
+index 142927e5f485..fb3ef3917fb1 100644
+--- a/arch/arm/boot/bootp/init.S
++++ b/arch/arm/boot/bootp/init.S
+@@ -16,7 +16,7 @@
+ * size immediately following the kernel, we could build this into
+ * a binary blob, and concatenate the zImage using the cat command.
+ */
+- .section .start,#alloc,#execinstr
++ .section .start, "ax"
+ .type _start, #function
+ .globl _start
+
+diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S
+index 88e2a88d324b..0e092c36da2f 100644
+--- a/arch/arm/boot/compressed/big-endian.S
++++ b/arch/arm/boot/compressed/big-endian.S
+@@ -6,7 +6,7 @@
+ * Author: Nicolas Pitre
+ */
+
+- .section ".start", #alloc, #execinstr
++ .section ".start", "ax"
+
+ mrc p15, 0, r0, c1, c0, 0 @ read control reg
+ orr r0, r0, #(1 << 7) @ enable big endian mode
+diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
+index 9d5f9c099ba3..deece067e9bf 100644
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -114,7 +114,7 @@
+ #endif
+ .endm
+
+- .section ".start", #alloc, #execinstr
++ .section ".start", "ax"
+ /*
+ * sort out different calling conventions
+ */
+diff --git a/arch/arm/boot/compressed/piggy.S b/arch/arm/boot/compressed/piggy.S
+index 0284f84dcf38..27577644ee72 100644
+--- a/arch/arm/boot/compressed/piggy.S
++++ b/arch/arm/boot/compressed/piggy.S
+@@ -1,5 +1,5 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
+- .section .piggydata,#alloc
++ .section .piggydata, "a"
+ .globl input_data
+ input_data:
+ .incbin "arch/arm/boot/compressed/piggy_data"
+diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
+index 774ef1323554..4773490177c9 100644
+--- a/arch/arm/mm/proc-arm1020.S
++++ b/arch/arm/mm/proc-arm1020.S
+@@ -505,7 +505,7 @@ cpu_arm1020_name:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __arm1020_proc_info,#object
+ __arm1020_proc_info:
+diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
+index ae3c27b71594..928e8ca58f40 100644
+--- a/arch/arm/mm/proc-arm1020e.S
++++ b/arch/arm/mm/proc-arm1020e.S
+@@ -463,7 +463,7 @@ arm1020e_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __arm1020e_proc_info,#object
+ __arm1020e_proc_info:
+diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
+index dbb2413fe04d..385584c3d222 100644
+--- a/arch/arm/mm/proc-arm1022.S
++++ b/arch/arm/mm/proc-arm1022.S
+@@ -448,7 +448,7 @@ arm1022_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __arm1022_proc_info,#object
+ __arm1022_proc_info:
+diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
+index 72a5dafb8db6..122fd1246d85 100644
+--- a/arch/arm/mm/proc-arm1026.S
++++ b/arch/arm/mm/proc-arm1026.S
+@@ -442,7 +442,7 @@ arm1026_crval:
+ string cpu_arm1026_name, "ARM1026EJ-S"
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __arm1026_proc_info,#object
+ __arm1026_proc_info:
+diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
+index 3651cd70e418..c08cd1b0a1d0 100644
+--- a/arch/arm/mm/proc-arm720.S
++++ b/arch/arm/mm/proc-arm720.S
+@@ -186,7 +186,7 @@ arm720_crval:
+ * See <asm/procinfo.h> for a definition of this structure.
+ */
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
+ .type __\name\()_proc_info,#object
+diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
+index 024fb7732407..6eed87103b95 100644
+--- a/arch/arm/mm/proc-arm740.S
++++ b/arch/arm/mm/proc-arm740.S
+@@ -132,7 +132,7 @@ __arm740_setup:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+ .type __arm740_proc_info,#object
+ __arm740_proc_info:
+ .long 0x41807400
+diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
+index 25472d94426d..beb64a7ccb38 100644
+--- a/arch/arm/mm/proc-arm7tdmi.S
++++ b/arch/arm/mm/proc-arm7tdmi.S
+@@ -76,7 +76,7 @@ __arm7tdmi_setup:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro arm7tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
+ extra_hwcaps=0
+diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
+index 7a14bd4414c9..5d4319708362 100644
+--- a/arch/arm/mm/proc-arm920.S
++++ b/arch/arm/mm/proc-arm920.S
+@@ -448,7 +448,7 @@ arm920_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __arm920_proc_info,#object
+ __arm920_proc_info:
+diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
+index edccfcdcd551..7e22ca780b36 100644
+--- a/arch/arm/mm/proc-arm922.S
++++ b/arch/arm/mm/proc-arm922.S
+@@ -426,7 +426,7 @@ arm922_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __arm922_proc_info,#object
+ __arm922_proc_info:
+diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
+index 32a47cc19076..d343e77b8456 100644
+--- a/arch/arm/mm/proc-arm925.S
++++ b/arch/arm/mm/proc-arm925.S
+@@ -491,7 +491,7 @@ arm925_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
+ .type __\name\()_proc_info,#object
+diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
+index 96ea567d1b64..b2e83a04df21 100644
+--- a/arch/arm/mm/proc-arm926.S
++++ b/arch/arm/mm/proc-arm926.S
+@@ -474,7 +474,7 @@ arm926_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __arm926_proc_info,#object
+ __arm926_proc_info:
+diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
+index ee5b66f847c4..631ae64eeccd 100644
+--- a/arch/arm/mm/proc-arm940.S
++++ b/arch/arm/mm/proc-arm940.S
+@@ -344,7 +344,7 @@ __arm940_setup:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __arm940_proc_info,#object
+ __arm940_proc_info:
+diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
+index 7361837edc31..033ad7402d67 100644
+--- a/arch/arm/mm/proc-arm946.S
++++ b/arch/arm/mm/proc-arm946.S
+@@ -399,7 +399,7 @@ __arm946_setup:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+ .type __arm946_proc_info,#object
+ __arm946_proc_info:
+ .long 0x41009460
+diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
+index 7fac8c612134..2195468ccd76 100644
+--- a/arch/arm/mm/proc-arm9tdmi.S
++++ b/arch/arm/mm/proc-arm9tdmi.S
+@@ -70,7 +70,7 @@ __arm9tdmi_setup:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro arm9tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
+ .type __\name\()_proc_info, #object
+diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
+index 4001b73af4ee..fd3e5dd94e59 100644
+--- a/arch/arm/mm/proc-fa526.S
++++ b/arch/arm/mm/proc-fa526.S
+@@ -190,7 +190,7 @@ fa526_cr1_set:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __fa526_proc_info,#object
+ __fa526_proc_info:
+diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
+index 92e08bf37aad..685d324a74d3 100644
+--- a/arch/arm/mm/proc-feroceon.S
++++ b/arch/arm/mm/proc-feroceon.S
+@@ -584,7 +584,7 @@ feroceon_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req
+ .type __\name\()_proc_info,#object
+diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
+index 6f07d2ef4ff2..9182321a586a 100644
+--- a/arch/arm/mm/proc-mohawk.S
++++ b/arch/arm/mm/proc-mohawk.S
+@@ -429,7 +429,7 @@ mohawk_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __88sv331x_proc_info,#object
+ __88sv331x_proc_info:
+diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
+index ee2ce496239f..093ad2ceff28 100644
+--- a/arch/arm/mm/proc-sa110.S
++++ b/arch/arm/mm/proc-sa110.S
+@@ -199,7 +199,7 @@ sa110_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .type __sa110_proc_info,#object
+ __sa110_proc_info:
+diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
+index 222d5836f666..12b8fcab4b59 100644
+--- a/arch/arm/mm/proc-sa1100.S
++++ b/arch/arm/mm/proc-sa1100.S
+@@ -242,7 +242,7 @@ sa1100_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
+ .type __\name\()_proc_info,#object
+diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
+index 06d890a2342b..32f4df0915ef 100644
+--- a/arch/arm/mm/proc-v6.S
++++ b/arch/arm/mm/proc-v6.S
+@@ -264,7 +264,7 @@ v6_crval:
+ string cpu_elf_name, "v6"
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ /*
+ * Match any ARMv6 processor core.
+diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
+index 339eb17c9808..e351d682c2e3 100644
+--- a/arch/arm/mm/proc-v7.S
++++ b/arch/arm/mm/proc-v7.S
+@@ -637,7 +637,7 @@ __v7_setup_stack:
+ string cpu_elf_name, "v7"
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ /*
+ * Standard v7 proc info content
+diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
+index 293a4325b459..c2d3e85d3125 100644
+--- a/arch/arm/mm/proc-v7m.S
++++ b/arch/arm/mm/proc-v7m.S
+@@ -96,7 +96,7 @@ ENTRY(cpu_cm7_proc_fin)
+ ret lr
+ ENDPROC(cpu_cm7_proc_fin)
+
+- .section ".init.text", #alloc, #execinstr
++ .section ".init.text", "ax"
+
+ __v7m_cm7_setup:
+ mov r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP)
+@@ -180,7 +180,7 @@ ENDPROC(__v7m_setup)
+ string cpu_elf_name "v7m"
+ string cpu_v7m_name "ARMv7-M"
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0, proc_fns = v7m_processor_functions
+ .long 0 /* proc_info_list.__cpu_mm_mmu_flags */
+diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
+index 293dcc2c441f..da96e4de1353 100644
+--- a/arch/arm/mm/proc-xsc3.S
++++ b/arch/arm/mm/proc-xsc3.S
+@@ -499,7 +499,7 @@ xsc3_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req
+ .type __\name\()_proc_info,#object
+diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
+index 3d75b7972fd1..c7800c69921b 100644
+--- a/arch/arm/mm/proc-xscale.S
++++ b/arch/arm/mm/proc-xscale.S
+@@ -613,7 +613,7 @@ xscale_crval:
+
+ .align
+
+- .section ".proc.info.init", #alloc
++ .section ".proc.info.init", "a"
+
+ .macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
+ .type __\name\()_proc_info,#object
+--
+2.30.1
+
--- /dev/null
+From 12bea2007bfbdc1dd089dcd00694173bc9688b62 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 29 Apr 2020 01:20:11 +0100
+Subject: ARM: 8971/1: replace the sole use of a symbol with its definition
+
+From: Jian Cai <caij2003@gmail.com>
+
+commit a780e485b5768e78aef087502499714901b68cc4 upstream.
+
+ALT_UP_B macro sets symbol up_b_offset via .equ to an expression
+involving another symbol. The macro gets expanded twice when
+arch/arm/kernel/sleep.S is assembled, creating a scenario where
+up_b_offset is set to another expression involving symbols while its
+current value is based on symbols. LLVM integrated assembler does not
+allow such cases, and based on the documentation of binutils, "Values
+that are based on expressions involving other symbols are allowed, but
+some targets may restrict this to only being done once per assembly", so
+it may be better to avoid such cases as it is not clearly stated which
+targets should support or disallow them. The fix in this case is simple,
+as up_b_offset has only one use, so we can replace the use with the
+definition and get rid of up_b_offset.
+
+ Link:https://github.com/ClangBuiltLinux/linux/issues/920
+
+ Reviewed-by: Stefan Agner <stefan@agner.ch>
+
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Jian Cai <caij2003@gmail.com>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/include/asm/assembler.h | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
+index 1935b580f0e8..3ab133dfb249 100644
+--- a/arch/arm/include/asm/assembler.h
++++ b/arch/arm/include/asm/assembler.h
+@@ -270,10 +270,9 @@
+ .endif ;\
+ .popsection
+ #define ALT_UP_B(label) \
+- .equ up_b_offset, label - 9998b ;\
+ .pushsection ".alt.smp.init", "a" ;\
+ .long 9998b ;\
+- W(b) . + up_b_offset ;\
++ W(b) . + (label - 9998b) ;\
+ .popsection
+ #else
+ #define ALT_SMP(instr...)
+--
+2.30.1
+
--- /dev/null
+From 184d54cb3c79eab3a52e29dc05ceea1032a29ec4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 9 Jul 2020 11:17:36 +0100
+Subject: ARM: 8989/1: use .fpu assembler directives instead of assembler
+ arguments
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit a6c30873ee4a5cc0549c1973668156381ab2c1c4 upstream.
+
+Explicit FPU selection has been introduced in commit 1a6be26d5b1a
+("[ARM] Enable VFP to be built when non-VFP capable CPUs are selected")
+to make use of assembler mnemonics for VFP instructions.
+
+However, clang currently does not support passing assembler flags
+like this and errors out with:
+clang-10: error: the clang compiler does not support '-Wa,-mfpu=softvfp+vfp'
+
+Make use of the .fpu assembler directives to select the floating point
+hardware selectively. Also use the new unified assembler language
+mnemonics. This allows to build these procedures with Clang.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/762
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/vfp/Makefile | 2 --
+ arch/arm/vfp/vfphw.S | 30 ++++++++++++++++++++----------
+ 2 files changed, 20 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile
+index 94516c40ebd3..933cdd5ec252 100644
+--- a/arch/arm/vfp/Makefile
++++ b/arch/arm/vfp/Makefile
+@@ -7,6 +7,4 @@
+ # ccflags-y := -DDEBUG
+ # asflags-y := -DDEBUG
+
+-KBUILD_AFLAGS :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp -mfloat-abi=soft)
+-
+ obj-y += vfpmodule.o entry.o vfphw.o vfpsingle.o vfpdouble.o
+diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
+index f74a8f7e5f84..64868a89a59f 100644
+--- a/arch/arm/vfp/vfphw.S
++++ b/arch/arm/vfp/vfphw.S
+@@ -261,11 +261,14 @@ vfp_current_hw_state_address:
+
+ ENTRY(vfp_get_float)
+ tbl_branch r0, r3, #3
++ .fpu vfpv2
+ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+-1: mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
++1: vmov r0, s\dr
+ ret lr
+ .org 1b + 8
+-1: mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
++ .endr
++ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++1: vmov r0, s\dr
+ ret lr
+ .org 1b + 8
+ .endr
+@@ -273,11 +276,14 @@ ENDPROC(vfp_get_float)
+
+ ENTRY(vfp_put_float)
+ tbl_branch r1, r3, #3
++ .fpu vfpv2
+ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+-1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0
++1: vmov s\dr, r0
+ ret lr
+ .org 1b + 8
+-1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
++ .endr
++ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++1: vmov s\dr, r0
+ ret lr
+ .org 1b + 8
+ .endr
+@@ -285,15 +291,17 @@ ENDPROC(vfp_put_float)
+
+ ENTRY(vfp_get_double)
+ tbl_branch r0, r3, #3
++ .fpu vfpv2
+ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+-1: fmrrd r0, r1, d\dr
++1: vmov r0, r1, d\dr
+ ret lr
+ .org 1b + 8
+ .endr
+ #ifdef CONFIG_VFPv3
+ @ d16 - d31 registers
+- .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+-1: mrrc p11, 3, r0, r1, c\dr @ fmrrd r0, r1, d\dr
++ .fpu vfpv3
++ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++1: vmov r0, r1, d\dr
+ ret lr
+ .org 1b + 8
+ .endr
+@@ -307,15 +315,17 @@ ENDPROC(vfp_get_double)
+
+ ENTRY(vfp_put_double)
+ tbl_branch r2, r3, #3
++ .fpu vfpv2
+ .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+-1: fmdrr d\dr, r0, r1
++1: vmov d\dr, r0, r1
+ ret lr
+ .org 1b + 8
+ .endr
+ #ifdef CONFIG_VFPv3
++ .fpu vfpv3
+ @ d16 - d31 registers
+- .irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
+-1: mcrr p11, 3, r0, r1, c\dr @ fmdrr r0, r1, d\dr
++ .irp dr,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
++1: vmov d\dr, r0, r1
+ ret lr
+ .org 1b + 8
+ .endr
+--
+2.30.1
+
--- /dev/null
+From b5392758b8c45ec543b9d824d05b03b8bf83be52 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 9 Jul 2020 11:19:17 +0100
+Subject: ARM: 8990/1: use VFP assembler mnemonics in register load/store
+ macros
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit ee440336e5ef977c397afdb72cbf9c6b8effc8ea upstream.
+
+The integrated assembler of Clang 10 and earlier do not allow to access
+the VFP registers through the coprocessor load/store instructions:
+<instantiation>:4:6: error: invalid operand for instruction
+ LDC p11, cr0, [r10],#32*4 @ FLDMIAD r10!, {d0-d15}
+ ^
+
+This has been addressed with Clang 11 [0]. However, to support earlier
+versions of Clang and for better readability use of VFP assembler
+mnemonics still is preferred.
+
+Replace the coprocessor load/store instructions with explicit assembler
+mnemonics to accessing the floating point coprocessor registers. Use
+assembler directives to select the appropriate FPU version.
+
+This allows to build these macros with GNU assembler as well as with
+Clang's built-in assembler.
+
+[0] https://reviews.llvm.org/D59733
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/905
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/include/asm/vfpmacros.h | 19 +++++++++++--------
+ 1 file changed, 11 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
+index 628c336e8e3b..947ee5395e1f 100644
+--- a/arch/arm/include/asm/vfpmacros.h
++++ b/arch/arm/include/asm/vfpmacros.h
+@@ -19,23 +19,25 @@
+
+ @ read all the working registers back into the VFP
+ .macro VFPFLDMIA, base, tmp
++ .fpu vfpv2
+ #if __LINUX_ARM_ARCH__ < 6
+- LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
++ fldmiax \base!, {d0-d15}
+ #else
+- LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15}
++ vldmia \base!, {d0-d15}
+ #endif
+ #ifdef CONFIG_VFPv3
++ .fpu vfpv3
+ #if __LINUX_ARM_ARCH__ <= 6
+ ldr \tmp, =elf_hwcap @ may not have MVFR regs
+ ldr \tmp, [\tmp, #0]
+ tst \tmp, #HWCAP_VFPD32
+- ldclne p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
++ vldmiane \base!, {d16-d31}
+ addeq \base, \base, #32*4 @ step over unused register space
+ #else
+ VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
+ and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
+ cmp \tmp, #2 @ 32 x 64bit registers?
+- ldcleq p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d16-d31}
++ vldmiaeq \base!, {d16-d31}
+ addne \base, \base, #32*4 @ step over unused register space
+ #endif
+ #endif
+@@ -44,22 +46,23 @@
+ @ write all the working registers out of the VFP
+ .macro VFPFSTMIA, base, tmp
+ #if __LINUX_ARM_ARCH__ < 6
+- STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
++ fstmiax \base!, {d0-d15}
+ #else
+- STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
++ vstmia \base!, {d0-d15}
+ #endif
+ #ifdef CONFIG_VFPv3
++ .fpu vfpv3
+ #if __LINUX_ARM_ARCH__ <= 6
+ ldr \tmp, =elf_hwcap @ may not have MVFR regs
+ ldr \tmp, [\tmp, #0]
+ tst \tmp, #HWCAP_VFPD32
+- stclne p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
++ vstmiane \base!, {d16-d31}
+ addeq \base, \base, #32*4 @ step over unused register space
+ #else
+ VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
+ and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
+ cmp \tmp, #2 @ 32 x 64bit registers?
+- stcleq p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d16-d31}
++ vstmiaeq \base!, {d16-d31}
+ addne \base, \base, #32*4 @ step over unused register space
+ #endif
+ #endif
+--
+2.30.1
+
--- /dev/null
+From 24c661f203ea6f3af0495effbff3311408e225aa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 9 Jul 2020 11:21:27 +0100
+Subject: ARM: 8991/1: use VFP assembler mnemonics if available
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit 2cbd1cc3dcd3e84be1fc1987da24b190ddf24a70 upstream.
+
+The integrated assembler of Clang 10 and earlier do not allow to access
+the VFP registers through the coprocessor load/store instructions:
+arch/arm/vfp/vfpmodule.c:342:2: error: invalid operand for instruction
+ fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK));
+ ^
+arch/arm/vfp/vfpinstr.h:79:6: note: expanded from macro 'fmxr'
+ asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0"
+ ^
+<inline asm>:1:6: note: instantiated into assembly here
+ mcr p10, 7, r0, cr8, cr0, 0 @ fmxr FPEXC, r0
+ ^
+
+This has been addressed with Clang 11 [0]. However, to support earlier
+versions of Clang and for better readability use of VFP assembler
+mnemonics still is preferred.
+
+Ideally we would replace this code with the unified assembler language
+mnemonics vmrs/vmsr on call sites along with .fpu assembler directives.
+The GNU assembler supports the .fpu directive at least since 2.17 (when
+documentation has been added). Since Linux requires binutils 2.21 it is
+safe to use .fpu directive. However, binutils does not allow to use
+FPINST or FPINST2 as an argument to vmrs/vmsr instructions up to
+binutils 2.24 (see binutils commit 16d02dc907c5):
+arch/arm/vfp/vfphw.S: Assembler messages:
+arch/arm/vfp/vfphw.S:162: Error: operand 0 must be FPSID or FPSCR pr FPEXC -- `vmsr FPINST,r6'
+arch/arm/vfp/vfphw.S:165: Error: operand 0 must be FPSID or FPSCR pr FPEXC -- `vmsr FPINST2,r8'
+arch/arm/vfp/vfphw.S:235: Error: operand 1 must be a VFP extension System Register -- `vmrs r3,FPINST'
+arch/arm/vfp/vfphw.S:238: Error: operand 1 must be a VFP extension System Register -- `vmrs r12,FPINST2'
+
+Use as-instr in Kconfig to check if FPINST/FPINST2 can be used. If they
+can be used make use of .fpu directives and UAL VFP mnemonics for
+register access.
+
+This allows to build vfpmodule.c with Clang and its integrated assembler.
+
+[0] https://reviews.llvm.org/D59733
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/905
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+[nd: adjusted hunk from arch/arm/Kconfig due to missing
+ commit 8a90a3228b6a ("arm: Unplug KVM from the build system")]
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/Kconfig | 1 +
+ arch/arm/Kconfig.assembler | 6 ++++++
+ arch/arm/include/asm/vfp.h | 2 ++
+ arch/arm/include/asm/vfpmacros.h | 12 +++++++++++-
+ arch/arm/vfp/vfphw.S | 1 +
+ arch/arm/vfp/vfpinstr.h | 23 +++++++++++++++++++----
+ 6 files changed, 40 insertions(+), 5 deletions(-)
+ create mode 100644 arch/arm/Kconfig.assembler
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 1877da816f65..5004a7871008 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -2198,3 +2198,4 @@ source "arch/arm/crypto/Kconfig"
+ endif
+
+ source "arch/arm/kvm/Kconfig"
++source "arch/arm/Kconfig.assembler"
+diff --git a/arch/arm/Kconfig.assembler b/arch/arm/Kconfig.assembler
+new file mode 100644
+index 000000000000..5cb31aae1188
+--- /dev/null
++++ b/arch/arm/Kconfig.assembler
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0
++
++config AS_VFP_VMRS_FPINST
++ def_bool $(as-instr,.fpu vfpv2\nvmrs r0$(comma)FPINST)
++ help
++ Supported by binutils >= 2.24 and LLVM integrated assembler.
+diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h
+index 7157d2a30a49..19928bfb4f9c 100644
+--- a/arch/arm/include/asm/vfp.h
++++ b/arch/arm/include/asm/vfp.h
+@@ -9,6 +9,7 @@
+ #ifndef __ASM_VFP_H
+ #define __ASM_VFP_H
+
++#ifndef CONFIG_AS_VFP_VMRS_FPINST
+ #define FPSID cr0
+ #define FPSCR cr1
+ #define MVFR1 cr6
+@@ -16,6 +17,7 @@
+ #define FPEXC cr8
+ #define FPINST cr9
+ #define FPINST2 cr10
++#endif
+
+ /* FPSID bits */
+ #define FPSID_IMPLEMENTER_BIT (24)
+diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
+index 947ee5395e1f..ba0d4cb5377e 100644
+--- a/arch/arm/include/asm/vfpmacros.h
++++ b/arch/arm/include/asm/vfpmacros.h
+@@ -8,7 +8,16 @@
+
+ #include <asm/vfp.h>
+
+-@ Macros to allow building with old toolkits (with no VFP support)
++#ifdef CONFIG_AS_VFP_VMRS_FPINST
++ .macro VFPFMRX, rd, sysreg, cond
++ vmrs\cond \rd, \sysreg
++ .endm
++
++ .macro VFPFMXR, sysreg, rd, cond
++ vmsr\cond \sysreg, \rd
++ .endm
++#else
++ @ Macros to allow building with old toolkits (with no VFP support)
+ .macro VFPFMRX, rd, sysreg, cond
+ MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg
+ .endm
+@@ -16,6 +25,7 @@
+ .macro VFPFMXR, sysreg, rd, cond
+ MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd
+ .endm
++#endif
+
+ @ read all the working registers back into the VFP
+ .macro VFPFLDMIA, base, tmp
+diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
+index 64868a89a59f..6155ffae8603 100644
+--- a/arch/arm/vfp/vfphw.S
++++ b/arch/arm/vfp/vfphw.S
+@@ -81,6 +81,7 @@
+ ENTRY(vfp_support_entry)
+ DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
+
++ .fpu vfpv2
+ ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions
+ and r3, r3, #MODE_MASK @ are supported in kernel mode
+ teq r3, #USR_MODE
+diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
+index 15b95b5ab97e..402b54d8fe28 100644
+--- a/arch/arm/vfp/vfpinstr.h
++++ b/arch/arm/vfp/vfpinstr.h
+@@ -65,10 +65,23 @@
+ #define FPSCR_C (1 << 29)
+ #define FPSCR_V (1 << 28)
+
+-/*
+- * Since we aren't building with -mfpu=vfp, we need to code
+- * these instructions using their MRC/MCR equivalents.
+- */
++#ifdef CONFIG_AS_VFP_VMRS_FPINST
++
++#define fmrx(_vfp_) ({ \
++ u32 __v; \
++ asm(".fpu vfpv2\n" \
++ "vmrs %0, " #_vfp_ \
++ : "=r" (__v) : : "cc"); \
++ __v; \
++ })
++
++#define fmxr(_vfp_,_var_) \
++ asm(".fpu vfpv2\n" \
++ "vmsr " #_vfp_ ", %0" \
++ : : "r" (_var_) : "cc")
++
++#else
++
+ #define vfpreg(_vfp_) #_vfp_
+
+ #define fmrx(_vfp_) ({ \
+@@ -82,6 +95,8 @@
+ asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
+ : : "r" (_var_) : "cc")
+
++#endif
++
+ u32 vfp_single_cpdo(u32 inst, u32 fpscr);
+ u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
+
+--
+2.30.1
+
--- /dev/null
+From 4860aa0d04ac9751f03bc543ddf86c5454acb244 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 17 Nov 2020 00:46:39 +0100
+Subject: ARM: 9025/1: Kconfig: CPU_BIG_ENDIAN depends on !LD_IS_LLD
+
+From: Nick Desaulniers <ndesaulniers@google.com>
+
+commit 28187dc8ebd938d574edfc6d9e0f9c51c21ff3f4 upstream.
+
+LLD does not yet support any big endian architectures. Make this config
+non-selectable when using LLD until LLD is fixed.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/965
+
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Tested-by: Nathan Chancellor <natechancellor@gmail.com>
+Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
+Reported-by: kbuild test robot <lkp@intel.com>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mm/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
+index b169e580bf82..6bd452c6005c 100644
+--- a/arch/arm/mm/Kconfig
++++ b/arch/arm/mm/Kconfig
+@@ -742,6 +742,7 @@ config SWP_EMULATE
+ config CPU_BIG_ENDIAN
+ bool "Build big-endian kernel"
+ depends on ARCH_SUPPORTS_BIG_ENDIAN
++ depends on !LD_IS_LLD
+ help
+ Say Y if you plan on running a kernel in big-endian mode.
+ Note that your board must be properly built and your board
+--
+2.30.1
+
--- /dev/null
+From 521b1c0f0533d30a90e816aef3c6ab3e3d2da5ff Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 17 Nov 2020 23:11:36 +0100
+Subject: ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler
+
+From: Jian Cai <jiancai@google.com>
+
+commit 3c9f5708b7aed6a963e2aefccbd1854802de163e upstream.
+
+This patch replaces 6 IWMMXT instructions Clang's integrated assembler
+does not support in iwmmxt.S using macros, while making sure GNU
+assembler still emit the same instructions. This should be easier than
+providing full IWMMXT support in Clang. This is one of the last bits of
+kernel code that could be compiled but not assembled with clang. Once
+all of it works with IAS, we no longer need to special-case 32-bit Arm
+in Kbuild, or turn off CONFIG_IWMMXT when build-testing.
+
+"Intel Wireless MMX Technology - Developer Guide - August, 2002" should
+be referenced for the encoding schemes of these extensions.
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/975
+
+Suggested-by: Nick Desaulniers <ndesaulniers@google.com>
+Suggested-by: Ard Biesheuvel <ardb@kernel.org>
+Acked-by: Ard Biesheuvel <ardb@kernel.org>
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Tested-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Jian Cai <jiancai@google.com>
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/kernel/iwmmxt.S | 89 ++++++++++++++++++++--------------------
+ arch/arm/kernel/iwmmxt.h | 47 +++++++++++++++++++++
+ 2 files changed, 92 insertions(+), 44 deletions(-)
+ create mode 100644 arch/arm/kernel/iwmmxt.h
+
+diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
+index 81cd4d43b3ec..830c4b3dfa9b 100644
+--- a/arch/arm/kernel/iwmmxt.S
++++ b/arch/arm/kernel/iwmmxt.S
+@@ -19,6 +19,7 @@
+ #include <asm/thread_info.h>
+ #include <asm/asm-offsets.h>
+ #include <asm/assembler.h>
++#include "iwmmxt.h"
+
+ #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
+ #define PJ4(code...) code
+@@ -116,33 +117,33 @@ concan_save:
+
+ concan_dump:
+
+- wstrw wCSSF, [r1, #MMX_WCSSF]
+- wstrw wCASF, [r1, #MMX_WCASF]
+- wstrw wCGR0, [r1, #MMX_WCGR0]
+- wstrw wCGR1, [r1, #MMX_WCGR1]
+- wstrw wCGR2, [r1, #MMX_WCGR2]
+- wstrw wCGR3, [r1, #MMX_WCGR3]
++ wstrw wCSSF, r1, MMX_WCSSF
++ wstrw wCASF, r1, MMX_WCASF
++ wstrw wCGR0, r1, MMX_WCGR0
++ wstrw wCGR1, r1, MMX_WCGR1
++ wstrw wCGR2, r1, MMX_WCGR2
++ wstrw wCGR3, r1, MMX_WCGR3
+
+ 1: @ MUP? wRn
+ tst r2, #0x2
+ beq 2f
+
+- wstrd wR0, [r1, #MMX_WR0]
+- wstrd wR1, [r1, #MMX_WR1]
+- wstrd wR2, [r1, #MMX_WR2]
+- wstrd wR3, [r1, #MMX_WR3]
+- wstrd wR4, [r1, #MMX_WR4]
+- wstrd wR5, [r1, #MMX_WR5]
+- wstrd wR6, [r1, #MMX_WR6]
+- wstrd wR7, [r1, #MMX_WR7]
+- wstrd wR8, [r1, #MMX_WR8]
+- wstrd wR9, [r1, #MMX_WR9]
+- wstrd wR10, [r1, #MMX_WR10]
+- wstrd wR11, [r1, #MMX_WR11]
+- wstrd wR12, [r1, #MMX_WR12]
+- wstrd wR13, [r1, #MMX_WR13]
+- wstrd wR14, [r1, #MMX_WR14]
+- wstrd wR15, [r1, #MMX_WR15]
++ wstrd wR0, r1, MMX_WR0
++ wstrd wR1, r1, MMX_WR1
++ wstrd wR2, r1, MMX_WR2
++ wstrd wR3, r1, MMX_WR3
++ wstrd wR4, r1, MMX_WR4
++ wstrd wR5, r1, MMX_WR5
++ wstrd wR6, r1, MMX_WR6
++ wstrd wR7, r1, MMX_WR7
++ wstrd wR8, r1, MMX_WR8
++ wstrd wR9, r1, MMX_WR9
++ wstrd wR10, r1, MMX_WR10
++ wstrd wR11, r1, MMX_WR11
++ wstrd wR12, r1, MMX_WR12
++ wstrd wR13, r1, MMX_WR13
++ wstrd wR14, r1, MMX_WR14
++ wstrd wR15, r1, MMX_WR15
+
+ 2: teq r0, #0 @ anything to load?
+ reteq lr @ if not, return
+@@ -150,30 +151,30 @@ concan_dump:
+ concan_load:
+
+ @ Load wRn
+- wldrd wR0, [r0, #MMX_WR0]
+- wldrd wR1, [r0, #MMX_WR1]
+- wldrd wR2, [r0, #MMX_WR2]
+- wldrd wR3, [r0, #MMX_WR3]
+- wldrd wR4, [r0, #MMX_WR4]
+- wldrd wR5, [r0, #MMX_WR5]
+- wldrd wR6, [r0, #MMX_WR6]
+- wldrd wR7, [r0, #MMX_WR7]
+- wldrd wR8, [r0, #MMX_WR8]
+- wldrd wR9, [r0, #MMX_WR9]
+- wldrd wR10, [r0, #MMX_WR10]
+- wldrd wR11, [r0, #MMX_WR11]
+- wldrd wR12, [r0, #MMX_WR12]
+- wldrd wR13, [r0, #MMX_WR13]
+- wldrd wR14, [r0, #MMX_WR14]
+- wldrd wR15, [r0, #MMX_WR15]
++ wldrd wR0, r0, MMX_WR0
++ wldrd wR1, r0, MMX_WR1
++ wldrd wR2, r0, MMX_WR2
++ wldrd wR3, r0, MMX_WR3
++ wldrd wR4, r0, MMX_WR4
++ wldrd wR5, r0, MMX_WR5
++ wldrd wR6, r0, MMX_WR6
++ wldrd wR7, r0, MMX_WR7
++ wldrd wR8, r0, MMX_WR8
++ wldrd wR9, r0, MMX_WR9
++ wldrd wR10, r0, MMX_WR10
++ wldrd wR11, r0, MMX_WR11
++ wldrd wR12, r0, MMX_WR12
++ wldrd wR13, r0, MMX_WR13
++ wldrd wR14, r0, MMX_WR14
++ wldrd wR15, r0, MMX_WR15
+
+ @ Load wCx
+- wldrw wCSSF, [r0, #MMX_WCSSF]
+- wldrw wCASF, [r0, #MMX_WCASF]
+- wldrw wCGR0, [r0, #MMX_WCGR0]
+- wldrw wCGR1, [r0, #MMX_WCGR1]
+- wldrw wCGR2, [r0, #MMX_WCGR2]
+- wldrw wCGR3, [r0, #MMX_WCGR3]
++ wldrw wCSSF, r0, MMX_WCSSF
++ wldrw wCASF, r0, MMX_WCASF
++ wldrw wCGR0, r0, MMX_WCGR0
++ wldrw wCGR1, r0, MMX_WCGR1
++ wldrw wCGR2, r0, MMX_WCGR2
++ wldrw wCGR3, r0, MMX_WCGR3
+
+ @ clear CUP/MUP (only if r1 != 0)
+ teq r1, #0
+diff --git a/arch/arm/kernel/iwmmxt.h b/arch/arm/kernel/iwmmxt.h
+new file mode 100644
+index 000000000000..fb627286f5bb
+--- /dev/null
++++ b/arch/arm/kernel/iwmmxt.h
+@@ -0,0 +1,47 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef __IWMMXT_H__
++#define __IWMMXT_H__
++
++.irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
++.set .LwR\b, \b
++.set .Lr\b, \b
++.endr
++
++.set .LwCSSF, 0x2
++.set .LwCASF, 0x3
++.set .LwCGR0, 0x8
++.set .LwCGR1, 0x9
++.set .LwCGR2, 0xa
++.set .LwCGR3, 0xb
++
++.macro wldrd, reg:req, base:req, offset:req
++.inst 0xedd00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
++.endm
++
++.macro wldrw, reg:req, base:req, offset:req
++.inst 0xfd900100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
++.endm
++
++.macro wstrd, reg:req, base:req, offset:req
++.inst 0xedc00100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
++.endm
++
++.macro wstrw, reg:req, base:req, offset:req
++.inst 0xfd800100 | (.L\reg << 12) | (.L\base << 16) | (\offset >> 2)
++.endm
++
++#ifdef __clang__
++
++#define wCon c1
++
++.macro tmrc, dest:req, control:req
++mrc p1, 0, \dest, \control, c0, 0
++.endm
++
++.macro tmcr, control:req, src:req
++mcr p1, 0, \src, \control, c0, 0
++.endm
++#endif
++
++#endif
+--
+2.30.1
+
--- /dev/null
+From bcb9290f858cb0b76e575035a223bbc0bf90ac03 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 Apr 2019 09:54:02 +0200
+Subject: ARM: mvebu: drop unnecessary label
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit 3ab2b5fdd1d8fa92dae631b913553e8798be23a7 upstream.
+
+The label mvebu_boot_wa_start is not necessary and causes a build
+issue when building with LLVM's integrated assembler:
+ AS arch/arm/mach-mvebu/pmsu_ll.o
+ arch/arm/mach-mvebu/pmsu_ll.S:59:1: error: invalid symbol redefinition
+ mvebu_boot_wa_start:
+ ^
+
+Drop the label.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Acked-by: Nicolas Pitre <nico@fluxnic.net>
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mach-mvebu/pmsu_ll.S | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
+index 88651221dbdd..c1fb713e9306 100644
+--- a/arch/arm/mach-mvebu/pmsu_ll.S
++++ b/arch/arm/mach-mvebu/pmsu_ll.S
+@@ -56,7 +56,6 @@ ENDPROC(armada_38x_cpu_resume)
+
+ /* The following code will be executed from SRAM */
+ ENTRY(mvebu_boot_wa_start)
+-mvebu_boot_wa_start:
+ ARM_BE8(setend be)
+ adr r0, 1f
+ ldr r0, [r0] @ load the address of the
+--
+2.30.1
+
--- /dev/null
+From d6fab7ec24d0ce832a2f50647f12bfc1144daaa1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 11 Apr 2019 09:54:03 +0200
+Subject: ARM: mvebu: prefix coprocessor operand with p
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit 969ad77c14ab34d0046b013f2502de72647711d1 upstream.
+
+In every other instance where mrc is used the coprocessor operand
+is prefix with p (e.g. p15). Use the p prefix in this case too.
+This fixes a build issue when using LLVM's integrated assembler:
+ arch/arm/mach-mvebu/coherency_ll.S:69:6: error: invalid operand for instruction
+ mrc 15, 0, r3, cr0, cr0, 5
+ ^
+ arch/arm/mach-mvebu/pmsu_ll.S:19:6: error: invalid operand for instruction
+ mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
+ ^
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Acked-by: Nicolas Pitre <nico@fluxnic.net>
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mach-mvebu/coherency_ll.S | 2 +-
+ arch/arm/mach-mvebu/pmsu_ll.S | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
+index 8b2fbc8b6bc6..2d962fe48821 100644
+--- a/arch/arm/mach-mvebu/coherency_ll.S
++++ b/arch/arm/mach-mvebu/coherency_ll.S
+@@ -66,7 +66,7 @@ ENDPROC(ll_get_coherency_base)
+ * fabric registers
+ */
+ ENTRY(ll_get_coherency_cpumask)
+- mrc 15, 0, r3, cr0, cr0, 5
++ mrc p15, 0, r3, cr0, cr0, 5
+ and r3, r3, #15
+ mov r2, #(1 << 24)
+ lsl r3, r2, r3
+diff --git a/arch/arm/mach-mvebu/pmsu_ll.S b/arch/arm/mach-mvebu/pmsu_ll.S
+index c1fb713e9306..7aae9a25cfeb 100644
+--- a/arch/arm/mach-mvebu/pmsu_ll.S
++++ b/arch/arm/mach-mvebu/pmsu_ll.S
+@@ -16,7 +16,7 @@
+ ENTRY(armada_38x_scu_power_up)
+ mrc p15, 4, r1, c15, c0 @ get SCU base address
+ orr r1, r1, #0x8 @ SCU CPU Power Status Register
+- mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
++ mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
+ and r0, r0, #15
+ add r1, r1, r0
+ mov r0, #0x0
+--
+2.30.1
+
--- /dev/null
+From b3a738560ac9caf0819092127b18b452067fe50e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 29 Mar 2020 22:33:14 +0200
+Subject: ARM: OMAP2+: drop unnecessary adrl
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit d85d5247885ef2e8192287b895c2e381fa931b0b upstream.
+
+The adrl instruction has been introduced with commit dd31394779aa ("ARM:
+omap3: Thumb-2 compatibility for sleep34xx.S"), back when this assembly
+file was considerably longer. Today adr seems to have enough reach, even
+when inserting about 60 instructions between the use site and the label.
+Replace adrl with conventional adr instruction.
+
+This allows to build this file using Clang's integrated assembler (which
+does not support the adrl pseudo instruction).
+
+Link: https://github.com/ClangBuiltLinux/linux/issues/430
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mach-omap2/sleep34xx.S | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index 4927304b5902..64f6f85bc613 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -86,7 +86,7 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
+ stmfd sp!, {lr} @ save registers on stack
+ /* Setup so that we will disable and enable l2 */
+ mov r1, #0x1
+- adrl r3, l2dis_3630_offset @ may be too distant for plain adr
++ adr r3, l2dis_3630_offset
+ ldr r2, [r3] @ value for offset
+ str r1, [r2, r3] @ write to l2dis_3630
+ ldmfd sp!, {pc} @ restore regs and return
+--
+2.30.1
+
--- /dev/null
+From c40d30cfa57dcf46d01f412fd777fb802ac2b034 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 May 2019 00:40:50 +0200
+Subject: ARM: use arch_extension directive instead of arch argument
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit 3fe1ee40b2a2db271513a498c475c13572dcb4c6 upstream.
+
+The LLVM Target parser currently does not allow to specify the security
+extension as part of -march (see also LLVM Bug 40186 [0]). When trying
+to use Clang with LLVM's integrated assembler, this leads to build
+errors such as this:
+ clang-8: error: the clang compiler does not support '-Wa,-march=armv7-a+sec'
+
+Use ".arch_extension sec" to enable the security extension in a more
+portable fasion. Also make sure to use ".arch armv7-a" in case a v6/v7
+multi-platform kernel is being built.
+
+Note that this is technically not exactly the same as the old code
+checked for availabilty of the security extension by calling as-instr.
+However, there are already other sites which use ".arch_extension sec"
+unconditionally, hence de-facto we need an assembler capable of
+".arch_extension sec" already today (arch/arm/mm/proc-v7.S). The
+arch extension "sec" is available since binutils 2.21 according to
+its documentation [1].
+
+[0] https://bugs.llvm.org/show_bug.cgi?id=40186
+[1] https://sourceware.org/binutils/docs-2.21/as/ARM-Options.html
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Acked-by: Mans Rullgard <mans@mansr.com>
+Acked-by: Arnd Bergmann <arnd@arndb.de>
+Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+[nd: adjusted arch/arm/mach-exynos/Makefile due to missing
+ commit 2997520c2d4e ("ARM: exynos: Set MCPM as mandatory for
+ Exynos542x/5800 SoCs")]
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mach-bcm/Makefile | 3 ---
+ arch/arm/mach-bcm/bcm_kona_smc.c | 2 --
+ arch/arm/mach-exynos/Makefile | 4 ----
+ arch/arm/mach-exynos/exynos-smc.S | 3 ++-
+ arch/arm/mach-exynos/sleep.S | 3 ++-
+ arch/arm/mach-highbank/Makefile | 3 ---
+ arch/arm/mach-highbank/smc.S | 3 ++-
+ arch/arm/mach-keystone/Makefile | 3 ---
+ arch/arm/mach-keystone/smc.S | 1 +
+ arch/arm/mach-omap2/Makefile | 8 --------
+ arch/arm/mach-omap2/omap-headsmp.S | 2 ++
+ arch/arm/mach-omap2/omap-smc.S | 3 ++-
+ arch/arm/mach-omap2/sleep33xx.S | 1 +
+ arch/arm/mach-omap2/sleep34xx.S | 2 ++
+ arch/arm/mach-omap2/sleep43xx.S | 2 ++
+ arch/arm/mach-omap2/sleep44xx.S | 3 +++
+ arch/arm/mach-tango/Makefile | 3 ---
+ arch/arm/mach-tango/smc.S | 2 ++
+ 18 files changed, 21 insertions(+), 30 deletions(-)
+
+diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
+index 8fd23b263c60..b59c813b1af4 100644
+--- a/arch/arm/mach-bcm/Makefile
++++ b/arch/arm/mach-bcm/Makefile
+@@ -40,9 +40,6 @@ obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
+
+ # Support for secure monitor traps
+ obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o
+-ifeq ($(call as-instr,.arch_extension sec,as_has_sec),as_has_sec)
+-CFLAGS_bcm_kona_smc.o += -Wa,-march=armv7-a+sec -DREQUIRES_SEC
+-endif
+
+ # BCM2835
+ obj-$(CONFIG_ARCH_BCM2835) += board_bcm2835.o
+diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c
+index a55a7ecf146a..541e850a736c 100644
+--- a/arch/arm/mach-bcm/bcm_kona_smc.c
++++ b/arch/arm/mach-bcm/bcm_kona_smc.c
+@@ -125,9 +125,7 @@ static int bcm_kona_do_smc(u32 service_id, u32 buffer_phys)
+ __asmeq("%2", "r4")
+ __asmeq("%3", "r5")
+ __asmeq("%4", "r6")
+-#ifdef REQUIRES_SEC
+ ".arch_extension sec\n"
+-#endif
+ " smc #0\n"
+ : "=r" (ip), "=r" (r0)
+ : "r" (r4), "r" (r5), "r" (r6)
+diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
+index cd00c82a1add..44de9f36fd1b 100644
+--- a/arch/arm/mach-exynos/Makefile
++++ b/arch/arm/mach-exynos/Makefile
+@@ -14,9 +14,5 @@ obj-$(CONFIG_PM_SLEEP) += suspend.o
+
+ obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+
+-plus_sec := $(call as-instr,.arch_extension sec,+sec)
+-AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
+-AFLAGS_sleep.o :=-Wa,-march=armv7-a$(plus_sec)
+-
+ obj-$(CONFIG_EXYNOS5420_MCPM) += mcpm-exynos.o
+ CFLAGS_mcpm-exynos.o += -march=armv7-a
+diff --git a/arch/arm/mach-exynos/exynos-smc.S b/arch/arm/mach-exynos/exynos-smc.S
+index d259532ba937..6da31e6a7acb 100644
+--- a/arch/arm/mach-exynos/exynos-smc.S
++++ b/arch/arm/mach-exynos/exynos-smc.S
+@@ -10,7 +10,8 @@
+ /*
+ * Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3)
+ */
+-
++ .arch armv7-a
++ .arch_extension sec
+ ENTRY(exynos_smc)
+ stmfd sp!, {r4-r11, lr}
+ dsb
+diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
+index 2783c3a0c06a..ed93f91853b8 100644
+--- a/arch/arm/mach-exynos/sleep.S
++++ b/arch/arm/mach-exynos/sleep.S
+@@ -44,7 +44,8 @@ ENTRY(exynos_cpu_resume)
+ ENDPROC(exynos_cpu_resume)
+
+ .align
+-
++ .arch armv7-a
++ .arch_extension sec
+ ENTRY(exynos_cpu_resume_ns)
+ mrc p15, 0, r0, c0, c0, 0
+ ldr r1, =CPU_MASK
+diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
+index 55840f414d3e..e7741b883d13 100644
+--- a/arch/arm/mach-highbank/Makefile
++++ b/arch/arm/mach-highbank/Makefile
+@@ -1,6 +1,3 @@
+ obj-y := highbank.o system.o smc.o
+
+-plus_sec := $(call as-instr,.arch_extension sec,+sec)
+-AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
+-
+ obj-$(CONFIG_PM_SLEEP) += pm.o
+diff --git a/arch/arm/mach-highbank/smc.S b/arch/arm/mach-highbank/smc.S
+index 407d17baaaa9..860a79135b7b 100644
+--- a/arch/arm/mach-highbank/smc.S
++++ b/arch/arm/mach-highbank/smc.S
+@@ -16,7 +16,8 @@
+ * the monitor API number.
+ * Function signature : void highbank_smc1(u32 fn, u32 arg)
+ */
+-
++ .arch armv7-a
++ .arch_extension sec
+ ENTRY(highbank_smc1)
+ stmfd sp!, {r4-r11, lr}
+ mov r12, r0
+diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
+index f8b0dccac8dc..739b38be5696 100644
+--- a/arch/arm/mach-keystone/Makefile
++++ b/arch/arm/mach-keystone/Makefile
+@@ -1,9 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-y := keystone.o smc.o
+
+-plus_sec := $(call as-instr,.arch_extension sec,+sec)
+-AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
+-
+ obj-$(CONFIG_SMP) += platsmp.o
+
+ # PM domain driver for Keystone SOCs
+diff --git a/arch/arm/mach-keystone/smc.S b/arch/arm/mach-keystone/smc.S
+index d15de8179fab..ec03dc499270 100644
+--- a/arch/arm/mach-keystone/smc.S
++++ b/arch/arm/mach-keystone/smc.S
+@@ -21,6 +21,7 @@
+ *
+ * Return: Non zero value on failure
+ */
++ .arch_extension sec
+ ENTRY(keystone_cpu_smc)
+ stmfd sp!, {r4-r11, lr}
+ smc #0
+diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
+index 01377c292db4..0b6c162764fb 100644
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -41,11 +41,6 @@ obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
+ obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
+ obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) sleep44xx.o
+
+-plus_sec := $(call as-instr,.arch_extension sec,+sec)
+-AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
+-AFLAGS_omap-smc.o :=-Wa,-march=armv7-a$(plus_sec)
+-AFLAGS_sleep44xx.o :=-Wa,-march=armv7-a$(plus_sec)
+-
+ # Functions loaded to SRAM
+ obj-$(CONFIG_SOC_OMAP2420) += sram242x.o
+ obj-$(CONFIG_SOC_OMAP2430) += sram243x.o
+@@ -95,9 +90,6 @@ obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
+ obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
+
+ AFLAGS_sleep24xx.o :=-Wa,-march=armv6
+-AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
+-AFLAGS_sleep33xx.o :=-Wa,-march=armv7-a$(plus_sec)
+-AFLAGS_sleep43xx.o :=-Wa,-march=armv7-a$(plus_sec)
+
+ endif
+
+diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
+index 4c6f14cf92a8..b26c0daaa3c1 100644
+--- a/arch/arm/mach-omap2/omap-headsmp.S
++++ b/arch/arm/mach-omap2/omap-headsmp.S
+@@ -58,6 +58,8 @@ ENDPROC(omap5_secondary_startup)
+ * omap5_secondary_startup if the primary CPU was put into HYP mode by
+ * the boot loader.
+ */
++ .arch armv7-a
++ .arch_extension sec
+ ENTRY(omap5_secondary_hyp_startup)
+ wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
+ ldr r0, [r2]
+diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S
+index 72506e6cf9e7..a14aee5e81d1 100644
+--- a/arch/arm/mach-omap2/omap-smc.S
++++ b/arch/arm/mach-omap2/omap-smc.S
+@@ -23,7 +23,8 @@
+ * link register "lr".
+ * Function signature : void omap_smc1(u32 fn, u32 arg)
+ */
+-
++ .arch armv7-a
++ .arch_extension sec
+ ENTRY(omap_smc1)
+ stmfd sp!, {r2-r12, lr}
+ mov r12, r0
+diff --git a/arch/arm/mach-omap2/sleep33xx.S b/arch/arm/mach-omap2/sleep33xx.S
+index 47a816468cdb..68fee339d3f1 100644
+--- a/arch/arm/mach-omap2/sleep33xx.S
++++ b/arch/arm/mach-omap2/sleep33xx.S
+@@ -24,6 +24,7 @@
+ #define BIT(nr) (1 << (nr))
+
+ .arm
++ .arch armv7-a
+ .align 3
+
+ ENTRY(am33xx_do_wfi)
+diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
+index 22daf4efed68..4927304b5902 100644
+--- a/arch/arm/mach-omap2/sleep34xx.S
++++ b/arch/arm/mach-omap2/sleep34xx.S
+@@ -97,6 +97,8 @@ ENDPROC(enable_omap3630_toggle_l2_on_restore)
+ *
+ * r0 = physical address of the parameters
+ */
++ .arch armv7-a
++ .arch_extension sec
+ ENTRY(save_secure_ram_context)
+ stmfd sp!, {r4 - r11, lr} @ save registers on stack
+ mov r3, r0 @ physical address of parameters
+diff --git a/arch/arm/mach-omap2/sleep43xx.S b/arch/arm/mach-omap2/sleep43xx.S
+index 5b9343b58fc7..31dda92d9d03 100644
+--- a/arch/arm/mach-omap2/sleep43xx.S
++++ b/arch/arm/mach-omap2/sleep43xx.S
+@@ -56,6 +56,8 @@
+ #define RTC_PMIC_EXT_WAKEUP_EN BIT(0)
+
+ .arm
++ .arch armv7-a
++ .arch_extension sec
+ .align 3
+
+ ENTRY(am43xx_do_wfi)
+diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
+index 0cae3b070208..fb559d3de1f2 100644
+--- a/arch/arm/mach-omap2/sleep44xx.S
++++ b/arch/arm/mach-omap2/sleep44xx.S
+@@ -21,8 +21,11 @@
+ #include "omap44xx.h"
+ #include "omap4-sar-layout.h"
+
++ .arch armv7-a
++
+ #if defined(CONFIG_SMP) && defined(CONFIG_PM)
+
++ .arch_extension sec
+ .macro DO_SMC
+ dsb
+ smc #0
+diff --git a/arch/arm/mach-tango/Makefile b/arch/arm/mach-tango/Makefile
+index da6c633d3cc0..97cd04508fa1 100644
+--- a/arch/arm/mach-tango/Makefile
++++ b/arch/arm/mach-tango/Makefile
+@@ -1,7 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0
+-plus_sec := $(call as-instr,.arch_extension sec,+sec)
+-AFLAGS_smc.o := -Wa,-march=armv7-a$(plus_sec)
+-
+ obj-y += setup.o smc.o
+ obj-$(CONFIG_SMP) += platsmp.o
+ obj-$(CONFIG_SUSPEND) += pm.o
+diff --git a/arch/arm/mach-tango/smc.S b/arch/arm/mach-tango/smc.S
+index 361a8dc89804..b1752aaa72bc 100644
+--- a/arch/arm/mach-tango/smc.S
++++ b/arch/arm/mach-tango/smc.S
+@@ -1,6 +1,8 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
+ #include <linux/linkage.h>
+
++ .arch armv7-a
++ .arch_extension sec
+ ENTRY(tango_smc)
+ push {lr}
+ mov ip, r1
+--
+2.30.1
+
--- /dev/null
+From 7c5d0d5f5f5695efee8e59a51485c14d125cfecd Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 17 Sep 2019 09:50:00 +0100
+Subject: crypto: arm/aes-ce - build for v8 architecture explicitly
+
+From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+
+commit 3aa6d4abd4ebf07c36e0a9a507af0311fcb267dc upstream.
+
+The NEON/Crypto Extensions based AES implementation for 32-bit ARM
+can be built in a kernel that targets ARMv6 CPUs and higher, even
+though the actual code will not be able to run on that generation,
+but it allows for a portable image to be generated that can will
+use the special instructions only when they are available.
+
+Since those instructions are part of a FPU profile rather than a
+CPU profile, we don't override the architecture in the assembler
+code, and most of the scalar code is simple enough to be ARMv6
+compatible. However, that changes with commit c61b1607ed4fbbf2,
+which introduces calls to the movw/movt instructions, which are
+v7+ only.
+
+So override the architecture in the .S file to armv8-a, which
+matches the architecture specification in the crypto-neon-fp-armv8
+FPU specificier that we already using. Note that using armv7-a
+here may trigger an issue with the upcoming Clang 10 release,
+which no longer permits .arch/.fpu combinations it views as
+incompatible.
+
+Reported-by: kbuild test robot <lkp@intel.com>
+Fixes: c61b1607ed4fbbf2 ("crypto: arm/aes-ce - implement ciphertext stealing ...")
+Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/crypto/aes-ce-core.S | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/crypto/aes-ce-core.S b/arch/arm/crypto/aes-ce-core.S
+index ba8e6a32fdc9..e912a73addbd 100644
+--- a/arch/arm/crypto/aes-ce-core.S
++++ b/arch/arm/crypto/aes-ce-core.S
+@@ -12,6 +12,7 @@
+ #include <asm/assembler.h>
+
+ .text
++ .arch armv8-a
+ .fpu crypto-neon-fp-armv8
+ .align 3
+
+--
+2.30.1
+
--- /dev/null
+From cb38e991ebc2cbe937192d52a33c40bbb1603829 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 2 Mar 2020 00:37:14 +0100
+Subject: crypto: arm/ghash-ce - define fpu before fpu registers are referenced
+
+From: Stefan Agner <stefan@agner.ch>
+
+commit 7548bf8c17d84607c106bd45d81834afd95a2edb upstream.
+
+Building ARMv7 with Clang's integrated assembler leads to errors such
+as:
+arch/arm/crypto/ghash-ce-core.S:34:11: error: register name expected
+ t3l .req d16
+ ^
+
+Since no FPU has selected yet Clang considers d16 not a valid register.
+Moving the FPU directive on-top allows Clang to parse the registers and
+allows to successfully build this file with Clang's integrated assembler.
+
+Signed-off-by: Stefan Agner <stefan@agner.ch>
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Tested-by: Nick Desaulniers <ndesaulniers@google.com>
+Acked-by: Ard Biesheuvel <ardb@kernel.org>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/crypto/ghash-ce-core.S | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/crypto/ghash-ce-core.S b/arch/arm/crypto/ghash-ce-core.S
+index e5d309d088fa..fca826e0bfc9 100644
+--- a/arch/arm/crypto/ghash-ce-core.S
++++ b/arch/arm/crypto/ghash-ce-core.S
+@@ -11,6 +11,9 @@
+ #include <linux/linkage.h>
+ #include <asm/assembler.h>
+
++ .arch armv8-a
++ .fpu crypto-neon-fp-armv8
++
+ SHASH .req q0
+ T1 .req q1
+ XL .req q2
+@@ -64,8 +67,6 @@
+ SHASH2_p64 .req d31
+
+ .text
+- .arch armv8-a
+- .fpu crypto-neon-fp-armv8
+
+ .macro __pmull_p64, rd, rn, rm, b1, b2, b3, b4
+ vmull.p64 \rd, \rn, \rm
+--
+2.30.1
+
--- /dev/null
+From d40b8e4adb006eb2bc2696779949cb07b19f950e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 16 Sep 2020 09:14:17 +0300
+Subject: crypto: arm/sha256-neon - avoid ADRL pseudo instruction
+
+From: Ard Biesheuvel <ardb@kernel.org>
+
+commit 54781938ec342cadbe2d76669ef8d3294d909974 upstream.
+
+The ADRL pseudo instruction is not an architectural construct, but a
+convenience macro that was supported by the ARM proprietary assembler
+and adopted by binutils GAS as well, but only when assembling in 32-bit
+ARM mode. Therefore, it can only be used in assembler code that is known
+to assemble in ARM mode only, but as it turns out, the Clang assembler
+does not implement ADRL at all, and so it is better to get rid of it
+entirely.
+
+So replace the ADRL instruction with a ADR instruction that refers to
+a nearer symbol, and apply the delta explicitly using an additional
+instruction.
+
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
+Tested-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/crypto/sha256-armv4.pl | 4 ++--
+ arch/arm/crypto/sha256-core.S_shipped | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/crypto/sha256-armv4.pl b/arch/arm/crypto/sha256-armv4.pl
+index a03cf4dfb781..d927483985c2 100644
+--- a/arch/arm/crypto/sha256-armv4.pl
++++ b/arch/arm/crypto/sha256-armv4.pl
+@@ -175,7 +175,6 @@ $code=<<___;
+ #else
+ .syntax unified
+ # ifdef __thumb2__
+-# define adrl adr
+ .thumb
+ # else
+ .code 32
+@@ -471,7 +470,8 @@ sha256_block_data_order_neon:
+ stmdb sp!,{r4-r12,lr}
+
+ sub $H,sp,#16*4+16
+- adrl $Ktbl,K256
++ adr $Ktbl,.Lsha256_block_data_order
++ sub $Ktbl,$Ktbl,#.Lsha256_block_data_order-K256
+ bic $H,$H,#15 @ align for 128-bit stores
+ mov $t2,sp
+ mov sp,$H @ alloca
+diff --git a/arch/arm/crypto/sha256-core.S_shipped b/arch/arm/crypto/sha256-core.S_shipped
+index 054aae0edfce..9deb515f3c9f 100644
+--- a/arch/arm/crypto/sha256-core.S_shipped
++++ b/arch/arm/crypto/sha256-core.S_shipped
+@@ -56,7 +56,6 @@
+ #else
+ .syntax unified
+ # ifdef __thumb2__
+-# define adrl adr
+ .thumb
+ # else
+ .code 32
+@@ -1885,7 +1884,8 @@ sha256_block_data_order_neon:
+ stmdb sp!,{r4-r12,lr}
+
+ sub r11,sp,#16*4+16
+- adrl r14,K256
++ adr r14,.Lsha256_block_data_order
++ sub r14,r14,#.Lsha256_block_data_order-K256
+ bic r11,r11,#15 @ align for 128-bit stores
+ mov r12,sp
+ mov sp,r11 @ alloca
+--
+2.30.1
+
--- /dev/null
+From 3ecddaefa61ca0527d685fda5833c9ff924eaf49 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 16 Sep 2020 09:14:18 +0300
+Subject: crypto: arm/sha512-neon - avoid ADRL pseudo instruction
+
+From: Ard Biesheuvel <ardb@kernel.org>
+
+commit 0f5e8323777bfc1c1d2cba71242db6a361de03b6 upstream.
+
+The ADRL pseudo instruction is not an architectural construct, but a
+convenience macro that was supported by the ARM proprietary assembler
+and adopted by binutils GAS as well, but only when assembling in 32-bit
+ARM mode. Therefore, it can only be used in assembler code that is known
+to assemble in ARM mode only, but as it turns out, the Clang assembler
+does not implement ADRL at all, and so it is better to get rid of it
+entirely.
+
+So replace the ADRL instruction with a ADR instruction that refers to
+a nearer symbol, and apply the delta explicitly using an additional
+instruction.
+
+Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
+Tested-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/crypto/sha512-armv4.pl | 4 ++--
+ arch/arm/crypto/sha512-core.S_shipped | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm/crypto/sha512-armv4.pl b/arch/arm/crypto/sha512-armv4.pl
+index 788c17b56ecc..2a0bdf7dd87c 100644
+--- a/arch/arm/crypto/sha512-armv4.pl
++++ b/arch/arm/crypto/sha512-armv4.pl
+@@ -212,7 +212,6 @@ $code=<<___;
+ #else
+ .syntax unified
+ # ifdef __thumb2__
+-# define adrl adr
+ .thumb
+ # else
+ .code 32
+@@ -602,7 +601,8 @@ sha512_block_data_order_neon:
+ dmb @ errata #451034 on early Cortex A8
+ add $len,$inp,$len,lsl#7 @ len to point at the end of inp
+ VFP_ABI_PUSH
+- adrl $Ktbl,K512
++ adr $Ktbl,.Lsha512_block_data_order
++ sub $Ktbl,$Ktbl,.Lsha512_block_data_order-K512
+ vldmia $ctx,{$A-$H} @ load context
+ .Loop_neon:
+ ___
+diff --git a/arch/arm/crypto/sha512-core.S_shipped b/arch/arm/crypto/sha512-core.S_shipped
+index 710ea309769e..cf5a7a70ff00 100644
+--- a/arch/arm/crypto/sha512-core.S_shipped
++++ b/arch/arm/crypto/sha512-core.S_shipped
+@@ -79,7 +79,6 @@
+ #else
+ .syntax unified
+ # ifdef __thumb2__
+-# define adrl adr
+ .thumb
+ # else
+ .code 32
+@@ -543,7 +542,8 @@ sha512_block_data_order_neon:
+ dmb @ errata #451034 on early Cortex A8
+ add r2,r1,r2,lsl#7 @ len to point at the end of inp
+ VFP_ABI_PUSH
+- adrl r3,K512
++ adr r3,.Lsha512_block_data_order
++ sub r3,r3,.Lsha512_block_data_order-K512
+ vldmia r0,{d16-d23} @ load context
+ .Loop_neon:
+ vshr.u64 d24,d20,#14 @ 0
+--
+2.30.1
+
--- /dev/null
+From 71c2f9f4eddafa1bc2b5f522f5eca4262c79c0b0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 11 Oct 2019 11:08:00 +0200
+Subject: crypto: arm - use Kconfig based compiler checks for crypto opcodes
+
+From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+
+commit b4d0c0aad57ac3bd1b5141bac5ab1ab1d5e442b3 upstream.
+
+Instead of allowing the Crypto Extensions algorithms to be selected when
+using a toolchain that does not support them, and complain about it at
+build time, use the information we have about the compiler to prevent
+them from being selected in the first place. Users that are stuck with
+a GCC version <4.8 are unlikely to care about these routines anyway, and
+it cleans up the Makefile considerably.
+
+While at it, add explicit 'armv8-a' CPU specifiers to the code that uses
+the 'crypto-neon-fp-armv8' FPU specifier so we don't regress Clang, which
+will complain about this in version 10 and later.
+
+Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/crypto/Kconfig | 14 +++++++------
+ arch/arm/crypto/Makefile | 32 ++++++-----------------------
+ arch/arm/crypto/crct10dif-ce-core.S | 1 +
+ arch/arm/crypto/ghash-ce-core.S | 1 +
+ arch/arm/crypto/sha1-ce-core.S | 1 +
+ arch/arm/crypto/sha2-ce-core.S | 1 +
+ 6 files changed, 18 insertions(+), 32 deletions(-)
+
+diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig
+index b8e69fe282b8..d97c99583877 100644
+--- a/arch/arm/crypto/Kconfig
++++ b/arch/arm/crypto/Kconfig
+@@ -30,7 +30,7 @@ config CRYPTO_SHA1_ARM_NEON
+
+ config CRYPTO_SHA1_ARM_CE
+ tristate "SHA1 digest algorithm (ARM v8 Crypto Extensions)"
+- depends on KERNEL_MODE_NEON
++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
+ select CRYPTO_SHA1_ARM
+ select CRYPTO_HASH
+ help
+@@ -39,7 +39,7 @@ config CRYPTO_SHA1_ARM_CE
+
+ config CRYPTO_SHA2_ARM_CE
+ tristate "SHA-224/256 digest algorithm (ARM v8 Crypto Extensions)"
+- depends on KERNEL_MODE_NEON
++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
+ select CRYPTO_SHA256_ARM
+ select CRYPTO_HASH
+ help
+@@ -87,7 +87,7 @@ config CRYPTO_AES_ARM_BS
+
+ config CRYPTO_AES_ARM_CE
+ tristate "Accelerated AES using ARMv8 Crypto Extensions"
+- depends on KERNEL_MODE_NEON
++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_SIMD
+ help
+@@ -96,7 +96,7 @@ config CRYPTO_AES_ARM_CE
+
+ config CRYPTO_GHASH_ARM_CE
+ tristate "PMULL-accelerated GHASH using NEON/ARMv8 Crypto Extensions"
+- depends on KERNEL_MODE_NEON
++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
+ select CRYPTO_HASH
+ select CRYPTO_CRYPTD
+ help
+@@ -107,12 +107,14 @@ config CRYPTO_GHASH_ARM_CE
+
+ config CRYPTO_CRCT10DIF_ARM_CE
+ tristate "CRCT10DIF digest algorithm using PMULL instructions"
+- depends on KERNEL_MODE_NEON && CRC_T10DIF
++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
++ depends on CRC_T10DIF
+ select CRYPTO_HASH
+
+ config CRYPTO_CRC32_ARM_CE
+ tristate "CRC32(C) digest algorithm using CRC and/or PMULL instructions"
+- depends on KERNEL_MODE_NEON && CRC32
++ depends on KERNEL_MODE_NEON && (CC_IS_CLANG || GCC_VERSION >= 40800)
++ depends on CRC32
+ select CRYPTO_HASH
+
+ config CRYPTO_CHACHA20_NEON
+diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile
+index bd5bceef0605..63b3eaef6c71 100644
+--- a/arch/arm/crypto/Makefile
++++ b/arch/arm/crypto/Makefile
+@@ -11,32 +11,12 @@ obj-$(CONFIG_CRYPTO_SHA256_ARM) += sha256-arm.o
+ obj-$(CONFIG_CRYPTO_SHA512_ARM) += sha512-arm.o
+ obj-$(CONFIG_CRYPTO_CHACHA20_NEON) += chacha20-neon.o
+
+-ce-obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
+-ce-obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
+-ce-obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
+-ce-obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
+-ce-obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o
+-crc-obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o
+-
+-ifneq ($(crc-obj-y)$(crc-obj-m),)
+-ifeq ($(call as-instr,.arch armv8-a\n.arch_extension crc,y,n),y)
+-ce-obj-y += $(crc-obj-y)
+-ce-obj-m += $(crc-obj-m)
+-else
+-$(warning These CRC Extensions modules need binutils 2.23 or higher)
+-$(warning $(crc-obj-y) $(crc-obj-m))
+-endif
+-endif
+-
+-ifneq ($(ce-obj-y)$(ce-obj-m),)
+-ifeq ($(call as-instr,.fpu crypto-neon-fp-armv8,y,n),y)
+-obj-y += $(ce-obj-y)
+-obj-m += $(ce-obj-m)
+-else
+-$(warning These ARMv8 Crypto Extensions modules need binutils 2.23 or higher)
+-$(warning $(ce-obj-y) $(ce-obj-m))
+-endif
+-endif
++obj-$(CONFIG_CRYPTO_AES_ARM_CE) += aes-arm-ce.o
++obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
++obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
++obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
++obj-$(CONFIG_CRYPTO_CRCT10DIF_ARM_CE) += crct10dif-arm-ce.o
++obj-$(CONFIG_CRYPTO_CRC32_ARM_CE) += crc32-arm-ce.o
+
+ aes-arm-y := aes-cipher-core.o aes-cipher-glue.o
+ aes-arm-bs-y := aes-neonbs-core.o aes-neonbs-glue.o
+diff --git a/arch/arm/crypto/crct10dif-ce-core.S b/arch/arm/crypto/crct10dif-ce-core.S
+index 16019b5961e7..4352fadcf0e1 100644
+--- a/arch/arm/crypto/crct10dif-ce-core.S
++++ b/arch/arm/crypto/crct10dif-ce-core.S
+@@ -78,6 +78,7 @@
+ #endif
+
+ .text
++ .arch armv8-a
+ .fpu crypto-neon-fp-armv8
+
+ arg1_low32 .req r0
+diff --git a/arch/arm/crypto/ghash-ce-core.S b/arch/arm/crypto/ghash-ce-core.S
+index 2f78c10b1881..e5d309d088fa 100644
+--- a/arch/arm/crypto/ghash-ce-core.S
++++ b/arch/arm/crypto/ghash-ce-core.S
+@@ -64,6 +64,7 @@
+ SHASH2_p64 .req d31
+
+ .text
++ .arch armv8-a
+ .fpu crypto-neon-fp-armv8
+
+ .macro __pmull_p64, rd, rn, rm, b1, b2, b3, b4
+diff --git a/arch/arm/crypto/sha1-ce-core.S b/arch/arm/crypto/sha1-ce-core.S
+index b623f51ccbcf..faec573c1931 100644
+--- a/arch/arm/crypto/sha1-ce-core.S
++++ b/arch/arm/crypto/sha1-ce-core.S
+@@ -13,6 +13,7 @@
+ #include <asm/assembler.h>
+
+ .text
++ .arch armv8-a
+ .fpu crypto-neon-fp-armv8
+
+ k0 .req q0
+diff --git a/arch/arm/crypto/sha2-ce-core.S b/arch/arm/crypto/sha2-ce-core.S
+index 87ec11a5f405..2135ebd8671c 100644
+--- a/arch/arm/crypto/sha2-ce-core.S
++++ b/arch/arm/crypto/sha2-ce-core.S
+@@ -13,6 +13,7 @@
+ #include <asm/assembler.h>
+
+ .text
++ .arch armv8-a
+ .fpu crypto-neon-fp-armv8
+
+ k0 .req q7
+--
+2.30.1
+
--- /dev/null
+From c66b1340b255d2539a74689f5d783cac1f5f0d55 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 23 Dec 2020 18:21:52 +0100
+Subject: i2c: rcar: optimize cacheline to minimize HW race condition
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+[ Upstream commit 25c2e0fb5fefb8d7847214cf114d94c7aad8e9ce ]
+
+'flags' and 'io' are needed first, so they should be at the beginning of
+the private struct.
+
+Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
+Signed-off-by: Wolfram Sang <wsa@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/i2c/busses/i2c-rcar.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
+index f9029800d399..3ea2ceec676c 100644
+--- a/drivers/i2c/busses/i2c-rcar.c
++++ b/drivers/i2c/busses/i2c-rcar.c
+@@ -117,6 +117,7 @@ enum rcar_i2c_type {
+ };
+
+ struct rcar_i2c_priv {
++ u32 flags;
+ void __iomem *io;
+ struct i2c_adapter adap;
+ struct i2c_msg *msg;
+@@ -127,7 +128,6 @@ struct rcar_i2c_priv {
+
+ int pos;
+ u32 icccr;
+- u32 flags;
+ u8 recovery_icmcr; /* protected by adapter lock */
+ enum rcar_i2c_type devtype;
+ struct i2c_client *slave;
+--
+2.30.1
+
--- /dev/null
+From fd9078303b2057f64668b51ede778aa2241fbde4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 30 Oct 2020 07:14:30 +0000
+Subject: i40e: Fix memory leak in i40e_probe
+
+From: Keita Suzuki <keitasuzuki.park@sslab.ics.keio.ac.jp>
+
+[ Upstream commit 58cab46c622d6324e47bd1c533693c94498e4172 ]
+
+Struct i40e_veb is allocated in function i40e_setup_pf_switch, and
+stored to an array field veb inside struct i40e_pf. However when
+i40e_setup_misc_vector fails, this memory leaks.
+
+Fix this by calling exit and teardown functions.
+
+Signed-off-by: Keita Suzuki <keitasuzuki.park@sslab.ics.keio.ac.jp>
+Tested-by: Tony Brelinski <tonyx.brelinski@intel.com>
+Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/intel/i40e/i40e_main.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
+index fe9da568ee19..1591f81d8ae3 100644
+--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
++++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
+@@ -13956,6 +13956,8 @@ static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+ if (err) {
+ dev_info(&pdev->dev,
+ "setup of misc vector failed: %d\n", err);
++ i40e_cloud_filter_exit(pf);
++ i40e_fdir_teardown(pf);
+ goto err_vsis;
+ }
+ }
+--
+2.30.1
+
--- /dev/null
+From 90b21ad4d35a3e025b9b3fd13fa3c5ac156ff722 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Apr 2020 15:14:15 -0700
+Subject: kbuild: add CONFIG_LD_IS_LLD
+
+From: Sami Tolvanen <samitolvanen@google.com>
+
+commit b744b43f79cc758127042e71f9ad7b1afda30f84 upstream.
+
+Similarly to the CC_IS_CLANG config, add LD_IS_LLD to avoid GNU ld
+specific logic such as ld-version or ld-ifversion and gain the
+ability to select potential features that depend on the linker at
+configuration time such as LTO.
+
+Signed-off-by: Sami Tolvanen <samitolvanen@google.com>
+Acked-by: Masahiro Yamada <masahiroy@kernel.org>
+[nc: Reword commit message]
+Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
+Tested-by: Sedat Dilek <sedat.dilek@gmail.com>
+Reviewed-by: Sedat Dilek <sedat.dilek@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ init/Kconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/init/Kconfig b/init/Kconfig
+index 5eb91dde4018..afb96e7bdd29 100644
+--- a/init/Kconfig
++++ b/init/Kconfig
+@@ -19,6 +19,9 @@ config GCC_VERSION
+ config CC_IS_CLANG
+ def_bool $(success,$(CC) --version | head -n 1 | grep -q clang)
+
++config LD_IS_LLD
++ def_bool $(success,$(LD) -v | head -n 1 | grep -q LLD)
++
+ config CLANG_VERSION
+ int
+ default $(shell,$(srctree)/scripts/clang-version.sh $(CC))
+--
+2.30.1
+
--- /dev/null
+From 581facfa38acbfd79612de1902e812059c6cf149 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 15 Jan 2020 11:30:07 +0000
+Subject: kbuild: Add support for 'as-instr' to be used in Kconfig files
+
+From: Catalin Marinas <catalin.marinas@arm.com>
+
+commit 42d519e3d0c071161d0a1c36e95a3743b113c590 upstream.
+
+Similar to 'cc-option' or 'ld-option', it is occasionally necessary to
+check whether the assembler supports certain ISA extensions. In the
+arm64 code we currently do this in Makefile with an additional define:
+
+lseinstr := $(call as-instr,.arch_extension lse,-DCONFIG_AS_LSE=1)
+
+Add the 'as-instr' option so that it can be used in Kconfig directly:
+
+ def_bool $(as-instr,.arch_extension lse)
+
+Acked-by: Masahiro Yamada <masahiroy@kernel.org>
+Reviewed-by: Vladimir Murzin <vladimir.murzin@arm.com>
+Tested-by: Vladimir Murzin <vladimir.murzin@arm.com>
+Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Will Deacon <will@kernel.org>
+Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ scripts/Kconfig.include | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/scripts/Kconfig.include b/scripts/Kconfig.include
+index 79455ad6b386..b762e02c0c31 100644
+--- a/scripts/Kconfig.include
++++ b/scripts/Kconfig.include
+@@ -26,5 +26,16 @@ cc-option = $(success,$(CC) -Werror $(CLANG_FLAGS) $(1) -S -x c /dev/null -o /de
+ # Return y if the linker supports <flag>, n otherwise
+ ld-option = $(success,$(LD) -v $(1))
+
++# $(as-instr,<instr>)
++# Return y if the assembler supports <instr>, n otherwise
++as-instr = $(success,printf "%b\n" "$(1)" | $(CC) $(CLANG_FLAGS) -c -x assembler -o /dev/null -)
++
++# check if $(CC) and $(LD) exist
++$(error-if,$(failure,command -v $(CC)),compiler '$(CC)' not found)
++$(error-if,$(failure,command -v $(LD)),linker '$(LD)' not found)
++
++# Fail if the linker is gold as it's not capable of linking the kernel proper
++$(error-if,$(success, $(LD) -v | grep -q gold), gold linker '$(LD)' not supported)
++
+ # gcc version including patch level
+ gcc-version := $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed 's/^0*//')
+--
+2.30.1
+
--- /dev/null
+From f8dd5179c8bf109b1b4ccf9600525b91f29683a2 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 18 Dec 2020 15:16:11 +0800
+Subject: mmc: mediatek: fix race condition between msdc_request_timeout and
+ irq
+
+From: Chaotian Jing <chaotian.jing@mediatek.com>
+
+[ Upstream commit 0354ca6edd464a2cf332f390581977b8699ed081 ]
+
+when get request SW timeout, if CMD/DAT xfer done irq coming right now,
+then there is race between the msdc_request_timeout work and irq handler,
+and the host->cmd and host->data may set to NULL in irq handler. also,
+current flow ensure that only one path can go to msdc_request_done(), so
+no need check the return value of cancel_delayed_work().
+
+Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
+Link: https://lore.kernel.org/r/20201218071611.12276-1-chaotian.jing@mediatek.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/mtk-sd.c | 18 ++++++++++--------
+ 1 file changed, 10 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
+index 9ecf86ba4bb0..967e47770af6 100644
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -928,13 +928,13 @@ static void msdc_track_cmd_data(struct msdc_host *host,
+ static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
+ {
+ unsigned long flags;
+- bool ret;
+
+- ret = cancel_delayed_work(&host->req_timeout);
+- if (!ret) {
+- /* delay work already running */
+- return;
+- }
++ /*
++ * No need check the return value of cancel_delayed_work, as only ONE
++ * path will go here!
++ */
++ cancel_delayed_work(&host->req_timeout);
++
+ spin_lock_irqsave(&host->lock, flags);
+ host->mrq = NULL;
+ spin_unlock_irqrestore(&host->lock, flags);
+@@ -952,7 +952,7 @@ static bool msdc_cmd_done(struct msdc_host *host, int events,
+ bool done = false;
+ bool sbc_error;
+ unsigned long flags;
+- u32 *rsp = cmd->resp;
++ u32 *rsp;
+
+ if (mrq->sbc && cmd == mrq->cmd &&
+ (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
+@@ -973,6 +973,7 @@ static bool msdc_cmd_done(struct msdc_host *host, int events,
+
+ if (done)
+ return true;
++ rsp = cmd->resp;
+
+ sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
+
+@@ -1154,7 +1155,7 @@ static void msdc_data_xfer_next(struct msdc_host *host,
+ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
+ struct mmc_request *mrq, struct mmc_data *data)
+ {
+- struct mmc_command *stop = data->stop;
++ struct mmc_command *stop;
+ unsigned long flags;
+ bool done;
+ unsigned int check_data = events &
+@@ -1170,6 +1171,7 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 events,
+
+ if (done)
+ return true;
++ stop = data->stop;
+
+ if (check_data || (stop && stop->error)) {
+ dev_dbg(host->dev, "DMA status: 0x%8X\n",
+--
+2.30.1
+
--- /dev/null
+From fe39d63e441f94d612645b1eafd9703eb070acfe Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 8 Dec 2020 21:35:27 +0100
+Subject: mmc: mxs-mmc: Fix a resource leak in an error handling path in
+ 'mxs_mmc_probe()'
+
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+
+[ Upstream commit 0bb7e560f821c7770973a94e346654c4bdccd42c ]
+
+If 'mmc_of_parse()' fails, we must undo the previous 'dma_request_chan()'
+call.
+
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Link: https://lore.kernel.org/r/20201208203527.49262-1-christophe.jaillet@wanadoo.fr
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/mmc/host/mxs-mmc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
+index add1e70195ea..7125687faf76 100644
+--- a/drivers/mmc/host/mxs-mmc.c
++++ b/drivers/mmc/host/mxs-mmc.c
+@@ -659,7 +659,7 @@ static int mxs_mmc_probe(struct platform_device *pdev)
+
+ ret = mmc_of_parse(mmc);
+ if (ret)
+- goto out_clk_disable;
++ goto out_free_dma;
+
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+--
+2.30.1
+
--- /dev/null
+From 52fcf02daf7bd05ba138747ac2087016122c3f94 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 2 Feb 2021 11:03:32 +0100
+Subject: PCI: Fix pci_register_io_range() memory leak
+
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+
+[ Upstream commit f6bda644fa3a7070621c3bf12cd657f69a42f170 ]
+
+Kmemleak reports:
+
+ unreferenced object 0xc328de40 (size 64):
+ comm "kworker/1:1", pid 21, jiffies 4294938212 (age 1484.670s)
+ hex dump (first 32 bytes):
+ 00 00 00 00 00 00 00 00 e0 d8 fc eb 00 00 00 00 ................
+ 00 00 10 fe 00 00 00 00 00 00 00 00 00 00 00 00 ................
+
+ backtrace:
+ [<ad758d10>] pci_register_io_range+0x3c/0x80
+ [<2c7f139e>] of_pci_range_to_resource+0x48/0xc0
+ [<f079ecc8>] devm_of_pci_get_host_bridge_resources.constprop.0+0x2ac/0x3ac
+ [<e999753b>] devm_of_pci_bridge_init+0x60/0x1b8
+ [<a895b229>] devm_pci_alloc_host_bridge+0x54/0x64
+ [<e451ddb0>] rcar_pcie_probe+0x2c/0x644
+
+In case a PCI host driver's probe is deferred, the same I/O range may be
+allocated again, and be ignored, causing a memory leak.
+
+Fix this by (a) letting logic_pio_register_range() return -EEXIST if the
+passed range already exists, so pci_register_io_range() will free it, and
+by (b) making pci_register_io_range() not consider -EEXIST an error
+condition.
+
+Link: https://lore.kernel.org/r/20210202100332.829047-1-geert+renesas@glider.be
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/pci.c | 4 ++++
+ lib/logic_pio.c | 3 +++
+ 2 files changed, 7 insertions(+)
+
+diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
+index 83fda1987d1f..9ebf32de8575 100644
+--- a/drivers/pci/pci.c
++++ b/drivers/pci/pci.c
+@@ -3817,6 +3817,10 @@ int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
+ ret = logic_pio_register_range(range);
+ if (ret)
+ kfree(range);
++
++ /* Ignore duplicates due to deferred probing */
++ if (ret == -EEXIST)
++ ret = 0;
+ #endif
+
+ return ret;
+diff --git a/lib/logic_pio.c b/lib/logic_pio.c
+index 905027574e5d..774bb02fff10 100644
+--- a/lib/logic_pio.c
++++ b/lib/logic_pio.c
+@@ -27,6 +27,8 @@ static DEFINE_MUTEX(io_range_mutex);
+ * @new_range: pointer to the IO range to be registered.
+ *
+ * Returns 0 on success, the error code in case of failure.
++ * If the range already exists, -EEXIST will be returned, which should be
++ * considered a success.
+ *
+ * Register a new IO range node in the IO range list.
+ */
+@@ -49,6 +51,7 @@ int logic_pio_register_range(struct logic_pio_hwaddr *new_range)
+ list_for_each_entry(range, &io_range_list, list) {
+ if (range->fwnode == new_range->fwnode) {
+ /* range already there */
++ ret = -EEXIST;
+ goto end_register;
+ }
+ if (range->flags == LOGIC_PIO_CPU_MMIO &&
+--
+2.30.1
+
--- /dev/null
+From 445713d5671a5ac188791bc365a39dfd93448488 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 20 Jan 2021 18:48:10 +0000
+Subject: PCI: mediatek: Add missing of_node_put() to fix reference leak
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Krzysztof Wilczyński <kw@linux.com>
+
+[ Upstream commit 42814c438aac79746d310f413a27d5b0b959c5de ]
+
+The for_each_available_child_of_node helper internally makes use of the
+of_get_next_available_child() which performs an of_node_get() on each
+iteration when searching for next available child node.
+
+Should an available child node be found, then it would return a device
+node pointer with reference count incremented, thus early return from
+the middle of the loop requires an explicit of_node_put() to prevent
+reference count leak.
+
+To stop the reference leak, explicitly call of_node_put() before
+returning after an error occurred.
+
+Link: https://lore.kernel.org/r/20210120184810.3068794-1-kw@linux.com
+Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/controller/pcie-mediatek.c | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
+index ca06d8bc01e7..066e9e00de11 100644
+--- a/drivers/pci/controller/pcie-mediatek.c
++++ b/drivers/pci/controller/pcie-mediatek.c
+@@ -1089,14 +1089,14 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
+ err = of_pci_get_devfn(child);
+ if (err < 0) {
+ dev_err(dev, "failed to parse devfn: %d\n", err);
+- return err;
++ goto error_put_node;
+ }
+
+ slot = PCI_SLOT(err);
+
+ err = mtk_pcie_parse_port(pcie, child, slot);
+ if (err)
+- return err;
++ goto error_put_node;
+ }
+
+ err = mtk_pcie_subsys_powerup(pcie);
+@@ -1112,6 +1112,9 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
+ mtk_pcie_subsys_powerdown(pcie);
+
+ return 0;
++error_put_node:
++ of_node_put(child);
++ return err;
+ }
+
+ static int mtk_pcie_request_resources(struct mtk_pcie *pcie)
+--
+2.30.1
+
--- /dev/null
+From 82c035767f180ca14c83623cfb1d912836cee2f3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 15 Jan 2021 22:24:35 +0100
+Subject: PCI: xgene-msi: Fix race in installing chained irq handler
+
+From: Martin Kaiser <martin@kaiser.cx>
+
+[ Upstream commit a93c00e5f975f23592895b7e83f35de2d36b7633 ]
+
+Fix a race where a pending interrupt could be received and the handler
+called before the handler's data has been setup, by converting to
+irq_set_chained_handler_and_data().
+
+See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained IRQ
+handler").
+
+Based on the mail discussion, it seems ok to drop the error handling.
+
+Link: https://lore.kernel.org/r/20210115212435.19940-3-martin@kaiser.cx
+Signed-off-by: Martin Kaiser <martin@kaiser.cx>
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pci/controller/pci-xgene-msi.c | 10 +++-------
+ 1 file changed, 3 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/pci/controller/pci-xgene-msi.c b/drivers/pci/controller/pci-xgene-msi.c
+index f4c02da84e59..0bfa5065b440 100644
+--- a/drivers/pci/controller/pci-xgene-msi.c
++++ b/drivers/pci/controller/pci-xgene-msi.c
+@@ -384,13 +384,9 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu)
+ if (!msi_group->gic_irq)
+ continue;
+
+- irq_set_chained_handler(msi_group->gic_irq,
+- xgene_msi_isr);
+- err = irq_set_handler_data(msi_group->gic_irq, msi_group);
+- if (err) {
+- pr_err("failed to register GIC IRQ handler\n");
+- return -EINVAL;
+- }
++ irq_set_chained_handler_and_data(msi_group->gic_irq,
++ xgene_msi_isr, msi_group);
++
+ /*
+ * Statically allocate MSI GIC IRQs to each CPU core.
+ * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated
+--
+2.30.1
+
--- /dev/null
+From bdd79248f4ba42920c563200eee1be4c5007585f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 30 Jan 2021 23:08:35 +1000
+Subject: powerpc: improve handling of unrecoverable system reset
+
+From: Nicholas Piggin <npiggin@gmail.com>
+
+[ Upstream commit 11cb0a25f71818ca7ab4856548ecfd83c169aa4d ]
+
+If an unrecoverable system reset hits in process context, the system
+does not have to panic. Similar to machine check, call nmi_exit()
+before die().
+
+Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20210130130852.2952424-26-npiggin@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/kernel/traps.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
+index 1b2d84cb373b..2379c4bf3979 100644
+--- a/arch/powerpc/kernel/traps.c
++++ b/arch/powerpc/kernel/traps.c
+@@ -433,8 +433,11 @@ void system_reset_exception(struct pt_regs *regs)
+ die("Unrecoverable nested System Reset", regs, SIGABRT);
+ #endif
+ /* Must die if the interrupt is not recoverable */
+- if (!(regs->msr & MSR_RI))
++ if (!(regs->msr & MSR_RI)) {
++ /* For the reason explained in die_mce, nmi_exit before die */
++ nmi_exit();
+ die("Unrecoverable System Reset", regs, SIGABRT);
++ }
+
+ if (!nested)
+ nmi_exit();
+--
+2.30.1
+
--- /dev/null
+From ea1a4d02a77e67b3e1bffe56125f3485ed93e2a0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 3 Nov 2020 15:35:06 +1100
+Subject: powerpc/pci: Add ppc_md.discover_phbs()
+
+From: Oliver O'Halloran <oohall@gmail.com>
+
+[ Upstream commit 5537fcb319d016ce387f818dd774179bc03217f5 ]
+
+On many powerpc platforms the discovery and initalisation of
+pci_controllers (PHBs) happens inside of setup_arch(). This is very early
+in boot (pre-initcalls) and means that we're initialising the PHB long
+before many basic kernel services (slab allocator, debugfs, a real ioremap)
+are available.
+
+On PowerNV this causes an additional problem since we map the PHB registers
+with ioremap(). As of commit d538aadc2718 ("powerpc/ioremap: warn on early
+use of ioremap()") a warning is printed because we're using the "incorrect"
+API to setup and MMIO mapping in searly boot. The kernel does provide
+early_ioremap(), but that is not intended to create long-lived MMIO
+mappings and a seperate warning is printed by generic code if
+early_ioremap() mappings are "leaked."
+
+This is all fixable with dumb hacks like using early_ioremap() to setup
+the initial mapping then replacing it with a real ioremap later on in
+boot, but it does raise the question: Why the hell are we setting up the
+PHB's this early in boot?
+
+The old and wise claim it's due to "hysterical rasins." Aside from amused
+grapes there doesn't appear to be any real reason to maintain the current
+behaviour. Already most of the newer embedded platforms perform PHB
+discovery in an arch_initcall and between the end of setup_arch() and the
+start of initcalls none of the generic kernel code does anything PCI
+related. On powerpc scanning PHBs occurs in a subsys_initcall so it should
+be possible to move the PHB discovery to a core, postcore or arch initcall.
+
+This patch adds the ppc_md.discover_phbs hook and a core_initcall stub that
+calls it. The core_initcalls are the earliest to be called so this will
+any possibly issues with dependency between initcalls. This isn't just an
+academic issue either since on pseries and PowerNV EEH init occurs in an
+arch_initcall and depends on the pci_controllers being available, similarly
+the creation of pci_dns occurs at core_initcall_sync (i.e. between core and
+postcore initcalls). These problems need to be addressed seperately.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
+[mpe: Make discover_phbs() static]
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/20201103043523.916109-1-oohall@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/include/asm/machdep.h | 3 +++
+ arch/powerpc/kernel/pci-common.c | 10 ++++++++++
+ 2 files changed, 13 insertions(+)
+
+diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
+index a47de82fb8e2..bda87cbf106d 100644
+--- a/arch/powerpc/include/asm/machdep.h
++++ b/arch/powerpc/include/asm/machdep.h
+@@ -71,6 +71,9 @@ struct machdep_calls {
+ int (*pcibios_root_bridge_prepare)(struct pci_host_bridge
+ *bridge);
+
++ /* finds all the pci_controllers present at boot */
++ void (*discover_phbs)(void);
++
+ /* To setup PHBs when using automatic OF platform driver for PCI */
+ int (*pci_setup_phb)(struct pci_controller *host);
+
+diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
+index 88e4f69a09e5..74628aca2bf1 100644
+--- a/arch/powerpc/kernel/pci-common.c
++++ b/arch/powerpc/kernel/pci-common.c
+@@ -1671,3 +1671,13 @@ static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
+ }
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
+ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
++
++
++static int __init discover_phbs(void)
++{
++ if (ppc_md.discover_phbs)
++ ppc_md.discover_phbs();
++
++ return 0;
++}
++core_initcall(discover_phbs);
+--
+2.30.1
+
--- /dev/null
+From 4b1414df9616d2064424d9e3ca597829d601ba7b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 5 Feb 2021 04:14:52 -0500
+Subject: powerpc/perf: Record counter overflow always if SAMPLE_IP is unset
+
+From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
+
+[ Upstream commit d137845c973147a22622cc76c7b0bc16f6206323 ]
+
+While sampling for marked events, currently we record the sample only
+if the SIAR valid bit of Sampled Instruction Event Register (SIER) is
+set. SIAR_VALID bit is used for fetching the instruction address from
+Sampled Instruction Address Register(SIAR). But there are some
+usecases, where the user is interested only in the PMU stats at each
+counter overflow and the exact IP of the overflow event is not
+required. Dropping SIAR invalid samples will fail to record some of
+the counter overflows in such cases.
+
+Example of such usecase is dumping the PMU stats (event counts) after
+some regular amount of instructions/events from the userspace (ex: via
+ptrace). Here counter overflow is indicated to userspace via signal
+handler, and captured by monitoring and enabling I/O signaling on the
+event file descriptor. In these cases, we expect to get
+sample/overflow indication after each specified sample_period.
+
+Perf event attribute will not have PERF_SAMPLE_IP set in the
+sample_type if exact IP of the overflow event is not requested. So
+while profiling if SAMPLE_IP is not set, just record the counter
+overflow irrespective of SIAR_VALID check.
+
+Suggested-by: Michael Ellerman <mpe@ellerman.id.au>
+Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
+[mpe: Reflow comment and if formatting]
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
+Link: https://lore.kernel.org/r/1612516492-1428-1-git-send-email-atrajeev@linux.vnet.ibm.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/powerpc/perf/core-book3s.c | 19 +++++++++++++++----
+ 1 file changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
+index 70de13822828..091bdeaf02a3 100644
+--- a/arch/powerpc/perf/core-book3s.c
++++ b/arch/powerpc/perf/core-book3s.c
+@@ -2046,7 +2046,17 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
+ left += period;
+ if (left <= 0)
+ left = period;
+- record = siar_valid(regs);
++
++ /*
++ * If address is not requested in the sample via
++ * PERF_SAMPLE_IP, just record that sample irrespective
++ * of SIAR valid check.
++ */
++ if (event->attr.sample_type & PERF_SAMPLE_IP)
++ record = siar_valid(regs);
++ else
++ record = 1;
++
+ event->hw.last_period = event->hw.sample_period;
+ }
+ if (left < 0x80000000LL)
+@@ -2064,9 +2074,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
+ * MMCR2. Check attr.exclude_kernel and address to drop the sample in
+ * these cases.
+ */
+- if (event->attr.exclude_kernel && record)
+- if (is_kernel_addr(mfspr(SPRN_SIAR)))
+- record = 0;
++ if (event->attr.exclude_kernel &&
++ (event->attr.sample_type & PERF_SAMPLE_IP) &&
++ is_kernel_addr(mfspr(SPRN_SIAR)))
++ record = 0;
+
+ /*
+ * Finally record data if requested.
+--
+2.30.1
+
--- /dev/null
+From 5c170343efc901288ec0d3e4c3c816e18f02286a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 17 Feb 2021 07:13:02 +0100
+Subject: s390/smp: __smp_rescan_cpus() - move cpumask away from stack
+
+From: Heiko Carstens <hca@linux.ibm.com>
+
+[ Upstream commit 62c8dca9e194326802b43c60763f856d782b225c ]
+
+Avoid a potentially large stack frame and overflow by making
+"cpumask_t avail" a static variable. There is no concurrent
+access due to the existing locking.
+
+Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
+Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/s390/kernel/smp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
+index c47bd581a08a..bce678c7179c 100644
+--- a/arch/s390/kernel/smp.c
++++ b/arch/s390/kernel/smp.c
+@@ -751,7 +751,7 @@ static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail,
+ static int __smp_rescan_cpus(struct sclp_core_info *info, bool early)
+ {
+ struct sclp_core_entry *core;
+- cpumask_t avail;
++ static cpumask_t avail;
+ bool configured;
+ u16 core_id;
+ int nr, i;
+--
+2.30.1
+
--- /dev/null
+From 9de1e614b06f60e942f0eb943e0ae5055205352b Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 6 Feb 2021 22:46:00 -0600
+Subject: scsi: libiscsi: Fix iscsi_prep_scsi_cmd_pdu() error handling
+
+From: Mike Christie <michael.christie@oracle.com>
+
+[ Upstream commit d28d48c699779973ab9a3bd0e5acfa112bd4fdef ]
+
+If iscsi_prep_scsi_cmd_pdu() fails we try to add it back to the cmdqueue,
+but we leave it partially setup. We don't have functions that can undo the
+pdu and init task setup. We only have cleanup_task which can clean up both
+parts. So this has us just fail the cmd and go through the standard cleanup
+routine and then have the SCSI midlayer retry it like is done when it fails
+in the queuecommand path.
+
+Link: https://lore.kernel.org/r/20210207044608.27585-2-michael.christie@oracle.com
+Reviewed-by: Lee Duncan <lduncan@suse.com>
+Signed-off-by: Mike Christie <michael.christie@oracle.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/scsi/libiscsi.c | 11 +++--------
+ 1 file changed, 3 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/scsi/libiscsi.c b/drivers/scsi/libiscsi.c
+index 2e40fd78e7b3..81471c304991 100644
+--- a/drivers/scsi/libiscsi.c
++++ b/drivers/scsi/libiscsi.c
+@@ -1569,14 +1569,9 @@ static int iscsi_data_xmit(struct iscsi_conn *conn)
+ }
+ rc = iscsi_prep_scsi_cmd_pdu(conn->task);
+ if (rc) {
+- if (rc == -ENOMEM || rc == -EACCES) {
+- spin_lock_bh(&conn->taskqueuelock);
+- list_add_tail(&conn->task->running,
+- &conn->cmdqueue);
+- conn->task = NULL;
+- spin_unlock_bh(&conn->taskqueuelock);
+- goto done;
+- } else
++ if (rc == -ENOMEM || rc == -EACCES)
++ fail_scsi_task(conn->task, DID_IMM_RETRY);
++ else
+ fail_scsi_task(conn->task, DID_ABORT);
+ spin_lock_bh(&conn->taskqueuelock);
+ continue;
+--
+2.30.1
+
--- /dev/null
+From 4b3c19d45d265b9caf9fa8fea183de5b3dd3253f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 9 Feb 2021 10:22:01 +0300
+Subject: scsi: target: core: Add cmd length set before cmd complete
+
+From: Aleksandr Miloserdov <a.miloserdov@yadro.com>
+
+[ Upstream commit 1c73e0c5e54d5f7d77f422a10b03ebe61eaed5ad ]
+
+TCM doesn't properly handle underflow case for service actions. One way to
+prevent it is to always complete command with
+target_complete_cmd_with_length(), however it requires access to data_sg,
+which is not always available.
+
+This change introduces target_set_cmd_data_length() function which allows
+to set command data length before completing it.
+
+Link: https://lore.kernel.org/r/20210209072202.41154-2-a.miloserdov@yadro.com
+Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
+Reviewed-by: Bodo Stroesser <bostroesser@gmail.com>
+Signed-off-by: Aleksandr Miloserdov <a.miloserdov@yadro.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/target/target_core_transport.c | 15 +++++++++++----
+ include/target/target_core_backend.h | 1 +
+ 2 files changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c
+index f1b730b77a31..bdada97cd4fe 100644
+--- a/drivers/target/target_core_transport.c
++++ b/drivers/target/target_core_transport.c
+@@ -841,11 +841,9 @@ void target_complete_cmd(struct se_cmd *cmd, u8 scsi_status)
+ }
+ EXPORT_SYMBOL(target_complete_cmd);
+
+-void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int length)
++void target_set_cmd_data_length(struct se_cmd *cmd, int length)
+ {
+- if ((scsi_status == SAM_STAT_GOOD ||
+- cmd->se_cmd_flags & SCF_TREAT_READ_AS_NORMAL) &&
+- length < cmd->data_length) {
++ if (length < cmd->data_length) {
+ if (cmd->se_cmd_flags & SCF_UNDERFLOW_BIT) {
+ cmd->residual_count += cmd->data_length - length;
+ } else {
+@@ -855,6 +853,15 @@ void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int len
+
+ cmd->data_length = length;
+ }
++}
++EXPORT_SYMBOL(target_set_cmd_data_length);
++
++void target_complete_cmd_with_length(struct se_cmd *cmd, u8 scsi_status, int length)
++{
++ if (scsi_status == SAM_STAT_GOOD ||
++ cmd->se_cmd_flags & SCF_TREAT_READ_AS_NORMAL) {
++ target_set_cmd_data_length(cmd, length);
++ }
+
+ target_complete_cmd(cmd, scsi_status);
+ }
+diff --git a/include/target/target_core_backend.h b/include/target/target_core_backend.h
+index 51b6f50eabee..0deeff9b4496 100644
+--- a/include/target/target_core_backend.h
++++ b/include/target/target_core_backend.h
+@@ -69,6 +69,7 @@ int transport_backend_register(const struct target_backend_ops *);
+ void target_backend_unregister(const struct target_backend_ops *);
+
+ void target_complete_cmd(struct se_cmd *, u8);
++void target_set_cmd_data_length(struct se_cmd *, int);
+ void target_complete_cmd_with_length(struct se_cmd *, u8, int);
+
+ void transport_copy_sense_to_cmd(struct se_cmd *, unsigned char *);
+--
+2.30.1
+
--- /dev/null
+From 7dcfeb52db621ca0d465857a38402e6dc6d7c9fa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 9 Feb 2021 10:22:02 +0300
+Subject: scsi: target: core: Prevent underflow for service actions
+
+From: Aleksandr Miloserdov <a.miloserdov@yadro.com>
+
+[ Upstream commit 14d24e2cc77411301e906a8cf41884739de192de ]
+
+TCM buffer length doesn't necessarily equal 8 + ADDITIONAL LENGTH which
+might be considered an underflow in case of Data-In size being greater than
+8 + ADDITIONAL LENGTH. So truncate buffer length to prevent underflow.
+
+Link: https://lore.kernel.org/r/20210209072202.41154-3-a.miloserdov@yadro.com
+Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com>
+Reviewed-by: Bodo Stroesser <bostroesser@gmail.com>
+Signed-off-by: Aleksandr Miloserdov <a.miloserdov@yadro.com>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/target/target_core_pr.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/target/target_core_pr.c b/drivers/target/target_core_pr.c
+index 10db5656fd5d..949879f2f1d1 100644
+--- a/drivers/target/target_core_pr.c
++++ b/drivers/target/target_core_pr.c
+@@ -3742,6 +3742,7 @@ core_scsi3_pri_read_keys(struct se_cmd *cmd)
+ spin_unlock(&dev->t10_pr.registration_lock);
+
+ put_unaligned_be32(add_len, &buf[4]);
++ target_set_cmd_data_length(cmd, 8 + add_len);
+
+ transport_kunmap_data_sg(cmd);
+
+@@ -3760,7 +3761,7 @@ core_scsi3_pri_read_reservation(struct se_cmd *cmd)
+ struct t10_pr_registration *pr_reg;
+ unsigned char *buf;
+ u64 pr_res_key;
+- u32 add_len = 16; /* Hardcoded to 16 when a reservation is held. */
++ u32 add_len = 0;
+
+ if (cmd->data_length < 8) {
+ pr_err("PRIN SA READ_RESERVATIONS SCSI Data Length: %u"
+@@ -3778,8 +3779,9 @@ core_scsi3_pri_read_reservation(struct se_cmd *cmd)
+ pr_reg = dev->dev_pr_res_holder;
+ if (pr_reg) {
+ /*
+- * Set the hardcoded Additional Length
++ * Set the Additional Length to 16 when a reservation is held
+ */
++ add_len = 16;
+ put_unaligned_be32(add_len, &buf[4]);
+
+ if (cmd->data_length < 22)
+@@ -3815,6 +3817,8 @@ core_scsi3_pri_read_reservation(struct se_cmd *cmd)
+ (pr_reg->pr_res_type & 0x0f);
+ }
+
++ target_set_cmd_data_length(cmd, 8 + add_len);
++
+ err:
+ spin_unlock(&dev->dev_reservation_lock);
+ transport_kunmap_data_sg(cmd);
+@@ -3833,7 +3837,7 @@ core_scsi3_pri_report_capabilities(struct se_cmd *cmd)
+ struct se_device *dev = cmd->se_dev;
+ struct t10_reservation *pr_tmpl = &dev->t10_pr;
+ unsigned char *buf;
+- u16 add_len = 8; /* Hardcoded to 8. */
++ u16 len = 8; /* Hardcoded to 8. */
+
+ if (cmd->data_length < 6) {
+ pr_err("PRIN SA REPORT_CAPABILITIES SCSI Data Length:"
+@@ -3845,7 +3849,7 @@ core_scsi3_pri_report_capabilities(struct se_cmd *cmd)
+ if (!buf)
+ return TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE;
+
+- put_unaligned_be16(add_len, &buf[0]);
++ put_unaligned_be16(len, &buf[0]);
+ buf[2] |= 0x10; /* CRH: Compatible Reservation Hanlding bit. */
+ buf[2] |= 0x08; /* SIP_C: Specify Initiator Ports Capable bit */
+ buf[2] |= 0x04; /* ATP_C: All Target Ports Capable bit */
+@@ -3874,6 +3878,8 @@ core_scsi3_pri_report_capabilities(struct se_cmd *cmd)
+ buf[4] |= 0x02; /* PR_TYPE_WRITE_EXCLUSIVE */
+ buf[5] |= 0x01; /* PR_TYPE_EXCLUSIVE_ACCESS_ALLREG */
+
++ target_set_cmd_data_length(cmd, len);
++
+ transport_kunmap_data_sg(cmd);
+
+ return 0;
+@@ -4034,6 +4040,7 @@ core_scsi3_pri_read_full_status(struct se_cmd *cmd)
+ * Set ADDITIONAL_LENGTH
+ */
+ put_unaligned_be32(add_len, &buf[4]);
++ target_set_cmd_data_length(cmd, 8 + add_len);
+
+ transport_kunmap_data_sg(cmd);
+
+--
+2.30.1
+
media-v4l-vsp1-fix-uif-null-pointer-access.patch
media-v4l-vsp1-fix-bru-null-pointer-access.patch
net-phy-fix-save-wrong-speed-and-duplex-problem-if-a.patch
+i2c-rcar-optimize-cacheline-to-minimize-hw-race-cond.patch
+udf-fix-silent-aed-taglocation-corruption.patch
+mmc-mxs-mmc-fix-a-resource-leak-in-an-error-handling.patch
+mmc-mediatek-fix-race-condition-between-msdc_request.patch
+powerpc-pci-add-ppc_md.discover_phbs.patch
+powerpc-improve-handling-of-unrecoverable-system-res.patch
+powerpc-perf-record-counter-overflow-always-if-sampl.patch
+sparc32-limit-memblock-allocation-to-low-memory.patch
+sparc64-use-arch_validate_flags-to-validate-adi-flag.patch
+pci-xgene-msi-fix-race-in-installing-chained-irq-han.patch
+pci-mediatek-add-missing-of_node_put-to-fix-referenc.patch
+pci-fix-pci_register_io_range-memory-leak.patch
+i40e-fix-memory-leak-in-i40e_probe.patch
+s390-smp-__smp_rescan_cpus-move-cpumask-away-from-st.patch
+scsi-libiscsi-fix-iscsi_prep_scsi_cmd_pdu-error-hand.patch
+scsi-target-core-add-cmd-length-set-before-cmd-compl.patch
+scsi-target-core-prevent-underflow-for-service-actio.patch
+arm-8788-1-ftrace-remove-old-mcount-support.patch
+arm-8800-1-use-choice-for-kernel-unwinders.patch
+arm-8827-1-fix-argument-count-to-match-macro-definit.patch
+arm-8828-1-uaccess-use-unified-assembler-language-sy.patch
+arm-8829-1-spinlock-use-unified-assembler-language-s.patch
+arm-8841-1-use-unified-assembler-in-macros.patch
+arm-8844-1-use-unified-assembler-in-assembly-files.patch
+arm-8852-1-uaccess-use-unified-assembler-language-sy.patch
+arm-mvebu-drop-unnecessary-label.patch
+arm-mvebu-prefix-coprocessor-operand-with-p.patch
+arm-use-arch_extension-directive-instead-of-arch-arg.patch
+crypto-arm-aes-ce-build-for-v8-architecture-explicit.patch
+crypto-arm-use-kconfig-based-compiler-checks-for-cry.patch
+arm-8929-1-use-apsr_nzcv-instead-of-r15-as-mrc-opera.patch
+arm-8933-1-replace-sun-solaris-style-flag-on-section.patch
+kbuild-add-support-for-as-instr-to-be-used-in-kconfi.patch
+crypto-arm-ghash-ce-define-fpu-before-fpu-registers-.patch
+arm-omap2-drop-unnecessary-adrl.patch
+arm-8971-1-replace-the-sole-use-of-a-symbol-with-its.patch
+kbuild-add-config_ld_is_lld.patch
+arm-8989-1-use-.fpu-assembler-directives-instead-of-.patch
+arm-8990-1-use-vfp-assembler-mnemonics-in-register-l.patch
+arm-8991-1-use-vfp-assembler-mnemonics-if-available.patch
+crypto-arm-sha256-neon-avoid-adrl-pseudo-instruction.patch
+crypto-arm-sha512-neon-avoid-adrl-pseudo-instruction.patch
+arm-9025-1-kconfig-cpu_big_endian-depends-on-ld_is_l.patch
+arm-9029-1-make-iwmmxt.s-support-clang-s-integrated-.patch
--- /dev/null
+From 41eb0a85d01ef907a3908c0f944d432c8719c003 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 5 Feb 2021 14:20:31 +0100
+Subject: sparc32: Limit memblock allocation to low memory
+
+From: Andreas Larsson <andreas@gaisler.com>
+
+[ Upstream commit bda166930c37604ffa93f2425426af6921ec575a ]
+
+Commit cca079ef8ac29a7c02192d2bad2ffe4c0c5ffdd0 changed sparc32 to use
+memblocks instead of bootmem, but also made high memory available via
+memblock allocation which does not work together with e.g. phys_to_virt
+and can lead to kernel panic.
+
+This changes back to only low memory being allocatable in the early
+stages, now using memblock allocation.
+
+Signed-off-by: Andreas Larsson <andreas@gaisler.com>
+Acked-by: Mike Rapoport <rppt@linux.ibm.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/sparc/mm/init_32.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
+index 92634d4e440c..89a9244f2cf0 100644
+--- a/arch/sparc/mm/init_32.c
++++ b/arch/sparc/mm/init_32.c
+@@ -199,6 +199,9 @@ unsigned long __init bootmem_init(unsigned long *pages_avail)
+ size = memblock_phys_mem_size() - memblock_reserved_size();
+ *pages_avail = (size >> PAGE_SHIFT) - high_pages;
+
++ /* Only allow low memory to be allocated via memblock allocation */
++ memblock_set_current_limit(max_low_pfn << PAGE_SHIFT);
++
+ return max_pfn;
+ }
+
+--
+2.30.1
+
--- /dev/null
+From 1de63d8a8f79e9b6f77113011b42ab75374b9420 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 23 Oct 2020 11:56:11 -0600
+Subject: sparc64: Use arch_validate_flags() to validate ADI flag
+
+From: Khalid Aziz <khalid.aziz@oracle.com>
+
+[ Upstream commit 147d8622f2a26ef34beacc60e1ed8b66c2fa457f ]
+
+When userspace calls mprotect() to enable ADI on an address range,
+do_mprotect_pkey() calls arch_validate_prot() to validate new
+protection flags. arch_validate_prot() for sparc looks at the first
+VMA associated with address range to verify if ADI can indeed be
+enabled on this address range. This has two issues - (1) Address
+range might cover multiple VMAs while arch_validate_prot() looks at
+only the first VMA, (2) arch_validate_prot() peeks at VMA without
+holding mmap lock which can result in race condition.
+
+arch_validate_flags() from commit c462ac288f2c ("mm: Introduce
+arch_validate_flags()") allows for VMA flags to be validated for all
+VMAs that cover the address range given by user while holding mmap
+lock. This patch updates sparc code to move the VMA check from
+arch_validate_prot() to arch_validate_flags() to fix above two
+issues.
+
+Suggested-by: Jann Horn <jannh@google.com>
+Suggested-by: Christoph Hellwig <hch@infradead.org>
+Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: Khalid Aziz <khalid.aziz@oracle.com>
+Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/sparc/include/asm/mman.h | 54 +++++++++++++++++++----------------
+ 1 file changed, 29 insertions(+), 25 deletions(-)
+
+diff --git a/arch/sparc/include/asm/mman.h b/arch/sparc/include/asm/mman.h
+index f94532f25db1..274217e7ed70 100644
+--- a/arch/sparc/include/asm/mman.h
++++ b/arch/sparc/include/asm/mman.h
+@@ -57,35 +57,39 @@ static inline int sparc_validate_prot(unsigned long prot, unsigned long addr)
+ {
+ if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_ADI))
+ return 0;
+- if (prot & PROT_ADI) {
+- if (!adi_capable())
+- return 0;
++ return 1;
++}
+
+- if (addr) {
+- struct vm_area_struct *vma;
++#define arch_validate_flags(vm_flags) arch_validate_flags(vm_flags)
++/* arch_validate_flags() - Ensure combination of flags is valid for a
++ * VMA.
++ */
++static inline bool arch_validate_flags(unsigned long vm_flags)
++{
++ /* If ADI is being enabled on this VMA, check for ADI
++ * capability on the platform and ensure VMA is suitable
++ * for ADI
++ */
++ if (vm_flags & VM_SPARC_ADI) {
++ if (!adi_capable())
++ return false;
+
+- vma = find_vma(current->mm, addr);
+- if (vma) {
+- /* ADI can not be enabled on PFN
+- * mapped pages
+- */
+- if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
+- return 0;
++ /* ADI can not be enabled on PFN mapped pages */
++ if (vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
++ return false;
+
+- /* Mergeable pages can become unmergeable
+- * if ADI is enabled on them even if they
+- * have identical data on them. This can be
+- * because ADI enabled pages with identical
+- * data may still not have identical ADI
+- * tags on them. Disallow ADI on mergeable
+- * pages.
+- */
+- if (vma->vm_flags & VM_MERGEABLE)
+- return 0;
+- }
+- }
++ /* Mergeable pages can become unmergeable
++ * if ADI is enabled on them even if they
++ * have identical data on them. This can be
++ * because ADI enabled pages with identical
++ * data may still not have identical ADI
++ * tags on them. Disallow ADI on mergeable
++ * pages.
++ */
++ if (vm_flags & VM_MERGEABLE)
++ return false;
+ }
+- return 1;
++ return true;
+ }
+ #endif /* CONFIG_SPARC64 */
+
+--
+2.30.1
+
--- /dev/null
+From e8b112ef4648071169693083f7f2eaab87b1b20f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Jan 2021 17:41:16 -0600
+Subject: udf: fix silent AED tagLocation corruption
+
+From: Steven J. Magnani <magnani@ieee.org>
+
+[ Upstream commit 63c9e47a1642fc817654a1bc18a6ec4bbcc0f056 ]
+
+When extending a file, udf_do_extend_file() may enter following empty
+indirect extent. At the end of udf_do_extend_file() we revert prev_epos
+to point to the last written extent. However if we end up not adding any
+further extent in udf_do_extend_file(), the reverting points prev_epos
+into the header area of the AED and following updates of the extents
+(in udf_update_extents()) will corrupt the header.
+
+Make sure that we do not follow indirect extent if we are not going to
+add any more extents so that returning back to the last written extent
+works correctly.
+
+Link: https://lore.kernel.org/r/20210107234116.6190-2-magnani@ieee.org
+Signed-off-by: Steven J. Magnani <magnani@ieee.org>
+Signed-off-by: Jan Kara <jack@suse.cz>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ fs/udf/inode.c | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/fs/udf/inode.c b/fs/udf/inode.c
+index 3bf89a633836..f5500d2a3879 100644
+--- a/fs/udf/inode.c
++++ b/fs/udf/inode.c
+@@ -540,11 +540,14 @@ static int udf_do_extend_file(struct inode *inode,
+
+ udf_write_aext(inode, last_pos, &last_ext->extLocation,
+ last_ext->extLength, 1);
++
+ /*
+- * We've rewritten the last extent but there may be empty
+- * indirect extent after it - enter it.
++ * We've rewritten the last extent. If we are going to add
++ * more extents, we may need to enter possible following
++ * empty indirect extent.
+ */
+- udf_next_aext(inode, last_pos, &tmploc, &tmplen, 0);
++ if (new_block_bytes || prealloc_len)
++ udf_next_aext(inode, last_pos, &tmploc, &tmplen, 0);
+ }
+
+ /* Managed to do everything necessary? */
+--
+2.30.1
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
